Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> digital implementation
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
digital implementation
"SoC-Encounter"
28nm
3D
3DIC
3D-IC
8.1
ARM
Avago
Brian Wallace
cadence
Cadence Encounter Power System
Cadence Online Support
CDNlive
CDNLive!
Conformal
CPF
CSV
CTE-TCL
DAC
DATE
dbGet
dbSet
design closure
design rules
DFM
digital
Digital Implementation forums
DRC
dynamic rail analysis
Early Rail Analysis
ECO
EDI
EDI 10.1
EDI 11
EDI 11.1
EDI System
EDI system Encounter Digital Implementation System
encounter
encounter 8.1
Encounter Digital Implementation
Encounter digital Implementation system
Encounter Digital Implementation System 8.1
encounter power system
Encounter Timing System
EPS
ETS
filler cells
First Encounter
five minute
five minute tutorial
five-minute
flip chip
Floorplanning
GigaOpt
Global Timing Debug
help
hierarchical design
IC Design
Industry Insights
IP
IR Drop
LEF
Logic Design
low power
Low-Power
LVS
Manufacturability Sign-off
mixed signal
mixed-signal
NanoRoute
noise analysis
PoP
power
power analysis
Power-Efficient Design
puzzler
Routing
RTL Compiler
screencast
scripting
SI analysis
signal integrity
Signoff Analysis
silicon realization
SoC
SoC-Encounter
SoC-Encounter 8.1
SOI
Sourcelink
STA
stacked die
static timing analysis
tapeout
TCL
timing convergence
TSV
tutorial
verification
Virtuoso
wirebond
Designer View – How GigaOpt in Encounter Digital Implementation (EDI) System 13.1 Boosts IC Design Quality
If you want to design faster chips in a shorter period of time, the new GigaOpt preRoute technology in the EDI System 13.1 release may be the solution. A detailed look at the GigaOpt preRoute technology came from a CDNLive Silicon Valley presentation March 12, 2013, given by Jack Benzel (right), expert...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 1 2013
CDNLive High-Performance Track: Do You Have What it Takes to Get Your High-Performance SoC to Market?
Implementing SoCs with embedded processors at advanced nodes has become increasingly difficult. This is due to the complexity of the design functionality as well as the low power and increased performance requirements driven by a plethora of end-user applications in modern hand-held devices. Path-breaking...
Posted to
Digital Implementation
(Weblog)
by
Vasu Madabushi
on Sun, Mar 10 2013
Five-Minute Tutorial: Create Encounter Power System (EPS) Power-Grid Views For Standard Cells
In today's tutorial, I'm giving you a sample EPS (Encounter Power System) script that you can use to generate power-grid views for your standard cells. Power-grid views are used during rail analysis, with IR-Drop and EM (electromigration/current density) being the two most popular analysis types...
Posted to
Digital Implementation
(Weblog)
by
Kari
on Fri, Feb 22 2013
CDNLive! 2012 Proceedings – Over 150 User Presentations on Design and Verification
A fantastic resource is available for chip and system designers -- proceedings from five of the CDNLive! Conferences held in 2012. By my count this includes over 150 user-authored presentations given at CDNLive! Silicon Valley (March 12-13), CDNLive! EMEA (May 6-8), CDNLive! Taiwan (July 11), CDNLive...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 9 2013
The Case for the Tiny Testcase
I often joke with customers that, although I realize they have to work on large designs, I do my best work on designs with just 2 or 3 instances. That's because I'm often trying to replicate an issue they've observed on their design and I'm attempting to reproduce that behavior in a smaller...
Posted to
Digital Implementation
(Weblog)
by
BobD
on Fri, Nov 16 2012
Transitioning Your LEF-Based EDI System Design Flow to OpenAccess
The trend of combining analog and digital circuits on a single chip has been growing for several years. More recently I'm seeing more and more designers improve their productivity by transitioning their designs to Open Access (OA) and taking advantage of the interoperability between Virtuoso and...
Posted to
Digital Implementation
(Weblog)
by
wally1
on Mon, Nov 12 2012
Simple Steps to Debug DRC Violations Undetected in EDI System
You've placed and routed your design in the Encounter Digital Implementation (EDI) System. It passed Verify Geometry and Verify Connectivity without a violation. Great! But when you run DRC signoff with your physical verification tool, you have violations related to the routing. What should you do...
Posted to
Digital Implementation
(Weblog)
by
wally1
on Mon, Sep 10 2012
In Case You Missed It – The Most Popular EDI System Knowledge Content Published in Recent Months
I mentioned in my first blog one of my roles in customer support is to identify and author knowledge content for Cadence Online Support ( http://support.cadence.com ). In this blog post I want to highlight some of the popular Encounter Design Implementation (EDI) System content published in recent months...
Posted to
Digital Implementation
(Weblog)
by
wally1
on Mon, Aug 6 2012
How To: Bring Up Encounter "man" Pages from a UNIX Prompt
Okay, this one is too cool not to share. The other day a customer and I were trying to understand a tool behavior better so we did what we all do in desperate times: We read the documentation. As straightforward as "reading the documentation" would seem, I bet no two users of the system interact...
Posted to
Digital Implementation
(Weblog)
by
BobD
on Wed, Aug 1 2012
10 Encounter Tips and Tricks You May Not Be Aware Of
In looking over the shoulders of Encounter users over the years I've found there's a bunch of little tips and tricks I use to make interacting with the tool a little easier that aren't necessarily immediately obvious. Here are some of the more common ones I used this week: When navigating...
Posted to
Digital Implementation
(Weblog)
by
BobD
on Fri, Jul 27 2012
Page 1 of 13 (128 items) 1
2
3
4
5
Next >
...
Last »