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design automation,memory ip

  • Interconnect IP Experts Answer Your Design, Verification Questions

    When it comes to electronics design and interconnects today, chaos is king. As the capacity of systems on chip soars, so too do the number of intellectual property (IP) blocks used to realize the design. And as that happens, the interconnection of the fabric and its verification rises in complexity and...
    Posted to The Fuller View (Weblog) by Brian Fuller on Mon, Nov 4 2013
  • What Do Applications Dream About?

    If you look back over the past two decades of processor-architecture design, you could say the period is defined broadly by two things: A vastly greater degree of design freedom The ability to dream bigger dreams Chris Rowen, the founder of Tensilica and now, since Cadence's acquisition of Tensilica...
    Posted to The Fuller View (Weblog) by Brian Fuller on Mon, Oct 21 2013
  • Clarifying the Changing Semiconductor Memory IP Landscape

    If you're staring out at the world of semiconductor memory IP and wondering how to make heads or tails of it, you've got sympathetic company. And yes, for electronics systems design engineers, it does seem like controlled chaos out there. But Cadence offered a little clarity this week with a...
    Posted to The Fuller View (Weblog) by Brian Fuller on Wed, Sep 18 2013
  • Live Q&A: Tackling Memory IP Challenges

    If you're a design engineer trying to navigate the world of changing intellectual property (IP) standards and how this affects your electronics system and subsystem designs, you have some choices: Ask your boss for a month off to bone up on all the new specifications, features, and functions and...
    Posted to The Fuller View (Weblog) by Brian Fuller on Thu, Sep 12 2013
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