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design IP,controller IP

  • Cadence Video Demonstrates PCIe Gen3 IP Silicon Performance
    It is not often that an IP provider gets to showcase their IP performance in a real product demo. Those laurels usually end up going to the end product that uses the IP. But a recent Cadence video features our PCI Express (PCIe) Gen 3 core running flawlessly in silicon in a real system. We thought we...
    Posted to Design IP (Weblog) by ashwinmatta on Mon, Aug 6 2012

  • Video, Part 2: Cadence Demonstrates PCIe Gen3 Advanced Features
    Welcome back for Part 2 of a two-part PCI-SIG video demo featuring Cadence’s PCI Express Gen3 Controller IP advanced capabilities, with a discussion on Single Root I/O Virtualization (SR-IOV). Part 1 was covered in a recent blog post . What is SR-IOV? Briefly, SR-IOV is a specification that allows...
    Posted to Design IP (Weblog) by StellaM1 on Wed, Aug 3 2011

  • Cadence Demonstrates PCI Express 3.0 Controller IP in Customer Silicon
    At the June 2011 PCI-SIG Developer's Conference, Cadence demonstrated Cadence Design IP for PCI Express 3.0 controller IP implemented as a high-performance, dual-mode, 128-bit data-path, x8 PCI Express 3.0 controller configuration in a customer's ASIC. The Cadence PCI Express 3.0 controller in...
    Posted to Design IP (Weblog) by StellaM1 on Thu, Jun 30 2011

  • New Memory Technologies, New Possibilities
    As a complete gadget geek, it’s always exciting to play with the latest technological toys. But if you stop to consider how each new wave of applications powered by these devices impacts the underlying SoC designs, you quickly realize that the memory and storage subsystem is now central to SoC...
    Posted to Design IP (Weblog) by Neil Hand on Mon, Apr 11 2011
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