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Q&A: Samsung’s Ana Hunter Offers Advance Look at 20nm

While all process node migrations have posed challenges, the move to 20nm may be more challenging than most. At this process node, lithography is so difficult that extra masks ( double patterning ) will be widely deployed. But despite the costs and challenges, the promise of higher performance and lower...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jul 11 2011
Tortoise Versus Hare … or How to Improve Your Time to Tapeout Using In-Design Signoff

Now that Wei Lii Tan has helped you with your New Year’s resolution to “create a chip that is so compelling …” in his previous blog , I would like to help you understand how Cadence is using our signoff qualified engines during the design implementation flow to reduce your time...

Posted to Digital Implementation (Weblog) by PeteMc on Wed, Feb 23 2011
Q&A: What Designers are Finding at 28nm – and How a “Unified” Digital Flow Can Help

Early adopters are starting to design at 28nm and are running into some challenges, according to Rahul Deokar, product management director for digital Silicon Realization at Cadence. In this interview he talks about challenges designers are experiencing due to design rules, lithography, low power, mixed...

Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 16 2011
What you didn’t know about DFM for advanced node designs: “In-route” is insufficient

Recently, there has been a lot of buzz about addressing DFM issues during routing. This is not a surprise as the economics of increased development cost of advanced process nodes and manufacturing has influenced dramatic changes to business models of several semiconductor companies. Due to the increasing...

Posted to Digital Implementation (Weblog) by mchacko on Fri, May 14 2010
Constraint Construction: What's Its Function? Part 4 of 4

This is the last in the series of Constraint Construction blogs ! Today we're going to go over DESIGN RULES and MODES OF OPERATION. DESIGN RULES: Follow them, or else... Often times, these rules are indeed set in the timing library. But perhaps you want sharper transitions in your design to reduce...

Posted to Digital Implementation (Weblog) by Thom Moore on Thu, Apr 9 2009

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design rules

Q&A: Samsung’s Ana Hunter Offers Advance Look at 20nm

Tortoise Versus Hare … or How to Improve Your Time to Tapeout Using In-Design Signoff

Q&A: What Designers are Finding at 28nm – and How a “Unified” Digital Flow Can Help

What you didn’t know about DFM for advanced node designs: “In-route” is insufficient

Constraint Construction: What's Its Function? Part 4 of 4