Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
More Products
OrCAD Products
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
IP Alliances
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Quicklinks
All Blogs
All Forums
Community Search
CDN
Live!
User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> design rules
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
All Blog Categories
Popular Tags
Allegro
ARM
Custom IC Design
DAC
Digital Implementation
e
EDA360
encounter
ESL
Functional Verification
Incisive
industry insights
Logic Design
Low power
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
SystemVerilog
TLM
UVM
verification
Virtuoso
Browse All Tags
Share
Email
Social Web
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
design rules
14nm
20 nm
20nm
28nm
3D IC
3D-IC
Adiva
advanced nodes
Allegro
Ana Hunter
Analog
ARM
ARM Cortex-M0
ARM Techcon
Azuro
Barkley
board
Cadence
Cadence 20nm
CDN Live
CDN Live!
CDNlive
circuit designers
clock concurrent optimization
collaboration
color-aware
colorization
colors
common platform
Cortex-M0
CPF
custom
custom methodology
custom/analog
DAC
DEM
Deokar
design enablement
design validation
DFM
DFM Coalition
DFMC
digital
Digital end-to-end flow
Digital Implementation
Digital Implementation forums
Double Patterning
DRC
DRC Plus
DRC+
dynamic rail analysis
ECO
EDA
EDI
EDI 10.1
EDI system
EDI system Encounter Digital Implementation System
EM Failures
encounter
Encounter Digital Implementation
Encounter Digital Implementation System 9.1
end-to-end
EPS
ETS
EUV
extraction
FinFets
Flex Models
FlexModels
gate first
gate last
Global Foundries
GlobalFoundries
GTC
HKMG
IBM
Industry Insights
lithography
Mixed-Signal
PCB assembly
PCB fabrication
PCB manufacturing
PCB test
physical verification
place and route
placement
power analysis
process variability
PVS
Rambus
rapid analog prototyping
routing
routing enablement
rtl compiler
Samsung
Samta Bansal
SI analysis
Si2
test chip
Virtuoso
Cadence and IBM Outline 20nm Custom/Analog EDA Flow Requirements
No 20nm IC design "solution" is complete without a custom/analog flow that can develop standard cells and analog/mixed-signal IP blocks. That custom/analog flow requires some changes to keep up with 20nm challenges such as double patterning and layout-dependent effects (LDE). A good overview...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 9 2012
CDNLive! Paper –Why Doesn’t My Board Work?
Why would a printed circuit board design go through a CAD system without a hitch, and then produce problems in fabrication or assembly - or worse, fail in the field? A paper at the recent CDNLive! Silicon Valley 2012 (Cadence user group conference) illustrated a number of ways this can happen, and showed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Apr 3 2012
On-Line Presentation: 20nm Design Challenges, and a Look Ahead to 14nm
The Common Platform Technology Forum held March 14 in Santa Clara, California, provided an updated look at process technology, design challenges, and ecosystem collaboration at 28nm and below. Much of the content is available throughout 2012 as part of a Virtual Technology Forum . Following is a report...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 19 2012
ARM TechCon Paper: Inside Story of a 20nm Test Chip Tapeout
In March 2011, ARM, Cadence and Samsung launched a collaborative effort to design a 20nm test chip based on nanoSTEP (nSTEP), a microcontroller reference platform based on the ARM Cortex-M0 processor. This chip taped out just two months later and was formally announced in July . At the recent ARM TechCon...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Dec 8 2011
GLOBALFOUNDRIES DRC+ Donation: New Era for DFM Standards?
DRC+, a pattern-matching design for manufacturability (DFM) technique developed by GLOBALFOUNDRIES in collaboration with Cadence, is heading for standardization through the Silicon Integration Initiative (Si2). As announced Oct. 20 at the Si2 Conference , GLOBALFOUNDRIES has donated DRC+ data structures...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Oct 23 2011
Q&A: A Look at 20nm Design Challenges and Solutions
The 20nm process node promises tremendous advantages in power, performance and design capacity, but also raises tough design challenges. These challenges include increased timing and power variability, complex layout rules, and incredibly large designs with massive amounts of IP. A major new challenge...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Sep 11 2011
GTC Presentation: Cadence Outlines Comprehensive 20nm Design Flow
The design and manufacturing challenges of 20nm ICs are formidable, and will not be solved by loose collections of point tools. At the recent Global Technology Conference ( GTC ), Cadence presented its view of 20nm challenges and previewed a comprehensive 20nm design methodology that encompasses custom...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 7 2011
GTC: GLOBALFOUNDRIES Charts Course for 28nm, 20nm and Beyond
The 28nm node is "fully enabled" and ready for production ramp-up, and 20nm early adopter flows are available now, according to GLOBALFOUNDRIES executives at the Global Technology Conference (GTC) in Santa Clara, California Aug. 30. In several morning sessions, speakers updated the company's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Aug 31 2011
Video: Easing the Design Challenges of Double Patterning at 20nm
Double patterning lithography will be essential at 20nm and below until at least 2014, according to Lars Liebman, distinguished engineer at IBM. But it need not be a huge burden for engineers. In a talk at the Cadence booth at the Design Automation Conference in June, and newly available in the video...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Aug 23 2011
Q&A: Samsung’s Ana Hunter Offers Advance Look at 20nm
While all process node migrations have posed challenges, the move to 20nm may be more challenging than most. At this process node, lithography is so difficult that extra masks ( double patterning ) will be widely deployed. But despite the costs and challenges, the promise of higher performance and lower...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jul 11 2011
Page 1 of 2 (14 items) 1
2
Next >