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  • meassuring delay in viva

    dear all, I would like to measure delay on signal "gap" simulated on two temp -40 and 125 with "trigger" option like: dly_fr=delay( v("gap") 0.75 1 "falling" v("gap") 0.75 2 "rising" 1 1 t "trigger") I am getting results like: time...
    Posted to Custom IC Design (Forum) by jerry124 on Tue, Nov 26 2013
  • delay in simulation initialization in ADE-XL

    Hi Andrew, We have a small but aggravating issue in running simulations on ADE-XL with IC6.1.5/MMSIM 10.11 When we run a simulation by pressing the green "play" button in the old fashioned test editor (opened from ADE-XL), the simulation starts to run instantly, as expected. But when we run...
    Posted to Custom IC Design (Forum) by aditeman on Wed, Nov 28 2012
  • FPGA PCB design considerations

    Hi, I am currently working on a data acquisition system that includes an ADC, a SRAM memory chip and an FPGA. The main idea here is to sample the waveforms with the ADC, feed the data to the memory chip, then use the FPGA and some USB device to send the data from the memory chip to the FPGA and then...
    Posted to PCB Design (Forum) by Lambros on Mon, Apr 18 2011
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