	Login with a Cadence account.
Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register \| Membership benefits

Get email delivery of the Cadence blog (individual posts).

Popular Tags

Browse All Tags

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

debugging

Develop for Debugability – Part 1

Debugging is the most time-critical activity of any verification engineer. Finding a bug is very often a combination of having a good hunch, experience, and the quality of testbench code that you need to analyze. Since having a good hunch and experience is something everyone needs to acquire for themselves...

Posted to Functional Verification (Weblog) by teamspecman on Mon, Apr 8 2013
Improve Debug Productivity - SimVision Video Series on YouTube

Most verification customers claim that they are spending over 50% of their verification effort in debug. If so, you should check out these latest SimVision debug videos since you will quickly see how SimVision can enable you to be much more productive in less than an hour after viewing the videos. Take...

Posted to Functional Verification (Weblog) by Karnane on Tue, Feb 5 2013
Functional Verification Survey -- Why Gate-Level Simulation is Increasing

In a recent webinar on increasing functional verification performance, the point was made that gate-level simulation usage is increasing. Wait a minute, I thought - haven't we spent the last two decades talking about raising the abstraction level for design and verification? While some IC verification...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 16 2013
Webinar Report: Speeding RTL and Gate-Level Simulation

Every verification team wants faster functional verification performance. Fortunately, there are many ways to achieve that. A recently archived Cadence webinar illustrates a number of techniques for speeding both RTL and gate-level simulation, including "out of the box" improvements to the...

Posted to Industry Insights (Weblog) by rgoering on Thu, Dec 13 2012
Archived Webinar: New Technology Attacks the Verification Debug Bottleneck

Verification debug hasn't exactly been a hotbed of technology innovation, even though verification teams report that debugging can consume more than 50% of the overall verification effort. A recently archived Cadence webinar reviews common debug challenges and shows how the new Incisive Debug Analyzer...

Posted to Industry Insights (Weblog) by rgoering on Thu, Nov 29 2012
Cadence Partner Udacity Brings Higher Education to the World

On-line education pioneer Udacity is partnering with Cadence to offer an upcoming free class in functional hardware verification - but Udacity's overall mission is quite a bit broader than that. Says David Evans, vice president of education at Udacity (right): "Our mission is to make high-quality...

Posted to Industry Insights (Weblog) by rgoering on Mon, Nov 26 2012
Recorded Webinar: Using Metric-Driven Verification and Formal Together For Higher Productivity

[Preface: the upcoming " Club Formal " on October 17 here at the Cadence San Jose campus will also touch on this topic - please join us! ] While it's now common knowledge that there are many benefits to using simulation technology within a metric-driven verification (MDV) flow , as it turns...

Posted to Functional Verification (Weblog) by TeamVerify on Wed, Oct 10 2012
User Presentation: Adapting a Specman “e” Simulation Testbench to Emulation

When Intel engineers were asked to verify one of the company's largest Many Integrated Core (MIC) designs, they faced a quandary. On one hand, they wanted the visibility and debug features provided by their Specman e language simulation environment. But they also wanted the much faster speeds provided...

Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 2 2012
In-Circuit Acceleration – A New IC Verification Use Model

Last year Cadence introduced the System Development Suite , a set of four connected hardware/software co-development platforms. Today (May 15, 2012) Cadence is announcing a new release of the System Development Suite that is highlighted by a new verification use model called in-circuit acceleration....

Posted to Industry Insights (Weblog) by rgoering on Tue, May 15 2012
DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!

In late April, a wealth of information on IC functional verification became available at the DVCon web site . Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can...

Posted to Industry Insights (Weblog) by rgoering on Tue, May 1 2012

Page 1 of 3 (29 items) 1 2 3 Next >

Popular Tags

Email

Share

Subscribe

Contact Us

debugging

Develop for Debugability – Part 1

Improve Debug Productivity - SimVision Video Series on YouTube

Functional Verification Survey -- Why Gate-Level Simulation is Increasing

Webinar Report: Speeding RTL and Gate-Level Simulation

Archived Webinar: New Technology Attacks the Verification Debug Bottleneck

Cadence Partner Udacity Brings Higher Education to the World

Recorded Webinar: Using Metric-Driven Verification and Formal Together For Higher Productivity

User Presentation: Adapting a Specman “e” Simulation Testbench to Emulation

In-Circuit Acceleration – A New IC Verification Use Model

DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!