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debug

Do You Have a DATE with Software? Cadence Does!

How important is the software market to Cadence and as an element of the EDA360 vision? Important enough that Cadence is sponsoring several relevant sessions at the upcoming Design, Automation, and Test in Europe (DATE) conference in Grenoble, March 14-18, 2011. If you're anywhere near Grenoble in...

Posted to System Design and Verification (Weblog) by Steve Brown on Mon, Feb 28 2011
S4D Workshop: System, Software, SoC and Silicon Debug

Debugging is challenging at every step in system design - whether for hardware or embedded software, or at the System Realization, SoC Realization, or Silicon Realization levels. A day-long workshop at the upcoming Design Automation and Test (DATE) conference in Grenoble, France March 14 is taking an...

Posted to Industry Insights (Weblog) by rgoering on Tue, Feb 22 2011
The Increasing Role of SystemC in System Design

Today's post is less technical and a bit more theoretical, but I promise that my next post will be more hands-on. As somebody working on virtual platforms in an EDA company, I regularly spend time talking to firmware and embedded software engineers with many different backgrounds. Every so often...

Posted to System Design and Verification (Weblog) by jasona on Tue, Feb 22 2011
IEEE SystemC Standard Revision – Here’s What to Expect

Standards are living, evolving entities, and SystemC -- standardized in 2005 as IEEE 1666 -- is no exception. This language, which has become indispensable for virtual platforms, high-level synthesis, and transaction-level modeling (TLM) design and verification, is undergoing a new revision this year...

Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 9 2011
The Role of Coverage in Formal Verification, Part 2 Continued…

Recall that three main questions need to be answered to attain coverage in formal verification: Part 1 of this series addressed, "How good are my formal constraints?" In Part 2 we showed debugging of over-constraining with help of examples, addressing the question, "How good is my verification...

Posted to Functional Verification (Weblog) by TeamVerify on Thu, Jan 27 2011
Support for e Language Macros in Amiq DVT Tool

DVT ( D esign and V erification T ools), a product offering from a 3rd party vendor, AMIQ , is for verification engineers working with e and SystemVerilog who are dissatisfied with the limitations of plain text editors and plain text searches (grep) when reading, writing or understanding source code...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Jan 25 2011
Achieve the Next Level of Verification Productivity with Specman Advanced Option

Advanced verification customers are seeing their verification environments getting more and more complex requiring millions of lines of code spread across hundreds, even thousands of files that are re-used from Block --> SoC --> System level. Today's design under test (DUT) can be extremely...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Jan 18 2011
There's Another Simulation Failure! New SimVision Features Can Help

Simulation failures are seen quite often in design verification. Fortunately, with the new Cadence Silicon Realization approach, you'll have the tools necessary to quickly get back to simulating. The complete solution for determining what is causing your simulation to fail is SimVision, part of the...

Posted to Functional Verification (Weblog) by jimkje on Wed, Jan 12 2011
My Reason For Choosing e – a Much More Advanced Verification Language. What’s Your Reason?

I'd like to share with you a story from many, many, many moons ago when I first evaluated e as a potential verification language solution for the company I was working for. At the time, our verification group was using the basic Verilog behavioural constructs for verification (memories to represent...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Jan 12 2011
Infinite Playbook for the Verification Superbowl

Its 4th and long, you're down by six, the clock is running out, and you are wary of a bug-blitz. What play do you call? With new approach defined by Silicon Realization, the updated Incisive Enterprise Simulator provides the new capabilities to finsh your drive, route the bugs, and win the verification...

Posted to Functional Verification (Weblog) by Team genIES on Mon, Jan 10 2011

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debug

Do You Have a DATE with Software? Cadence Does!

S4D Workshop: System, Software, SoC and Silicon Debug

The Increasing Role of SystemC in System Design

IEEE SystemC Standard Revision – Here’s What to Expect

The Role of Coverage in Formal Verification, Part 2 Continued…

Support for e Language Macros in Amiq DVT Tool

Achieve the Next Level of Verification Productivity with Specman Advanced Option

There's Another Simulation Failure! New SimVision Features Can Help

My Reason For Choosing e – a Much More Advanced Verification Language. What’s Your Reason?

Infinite Playbook for the Verification Superbowl