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debug,Functional Verification

How Do You Debug Your Testbench when it Won’t Stand Still?

The task of debugging a simulation problem in your design can be a difficult and time consuming task. These days, the verification engineer must also be able to debug very complex SystemVerilog testbenches too. This becomes difficult because of their dynamic nature -- they just won’t stand still...

Posted to Functional Verification (Weblog) by jimkje on Tue, Dec 14 2010
Verification Goldmine: 50 User Papers on Formal, Multi-Engine, and Assertion-Based Verification (ABV)

With all due respect to our Tech Pubs writers, Solutions Architects, and contributors to this blog, nothing beats hearing the experiences of end users applying a given tool or methodology to their real world challenges. Fortunately, Team Verify has been blessed with a generous and prolific community...

Posted to Functional Verification (Weblog) by TeamVerify on Tue, Nov 2 2010
Specman-SimVision webinar on April 22 (next week!)

We interrupt Corey's excellent "When Less Is More" series to announce a Specman-SimVision webinar next week, April 22 at 10:00AM Pacific time. In short, if you’ve been using Specview with Specman/ e and would like to learn all the key advantages of using the SimVision debug tool,...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Apr 13 2010
Built-in Message Logging – Part 2 of 2

[Team Specman welcomes back guest blogger, Michael Avery from our Services Group in the UK] Building on the Part 1 introduction to Specman’s messaging built-in infrastructure , allow me to share some tips on how to programmatically control and scale message display to help shorten your debug time...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Mar 17 2010
Tech Tip: Waving Specman Objects in SimVision

Did you know that you can wave Specman objects in IES-XL *and* also save the wave setup for automatically restarting the simulation? If not, this tech tip is for you! Here is the process: Step 0 – Once you are happy with your waveform setup, don’t forget the basic step of saving your mix...

Posted to Functional Verification (Weblog) by teamspecman on Fri, Jan 22 2010
Specman 9.2 Preview: Named Constraints

[Preface: all features in the 9.2 preview series are in Beta now. We invite you to sign-up for the beta program and give this feature a test drive!] [Team Specman welcomes Reuven Naveh from Specman R&D to introduce “his” new feature.] Abstract In Specman 9.2 we are extending the syntax...

Posted to Functional Verification (Weblog) by teamspecman on Fri, Aug 21 2009
FSM Mnemonics Maps (Enums) in SimVision Using Verilog 1364

The mighty FSM – you first learned it when you were a young pup at University (some of you still are!) and you use it day in and day out today. Such a simple concept – I’m in a known state and I will either remain here or move to a new state based on inputs – but a difficult one...

Posted to Functional Verification (Weblog) by Team genIES on Thu, Jul 23 2009
Enabling OVM Transaction Debug in SimVision Without Code Changes

Are you tired of putting print statements in your code to do debug? Do you work with designers who just want to use waveforms to debug testbench and design problems? There is a cool feature in the OVM library and Incisive Enterprise Simulator that comes to the rescue. It is the built-in OVM transaction...

Posted to Functional Verification (Weblog) by Team genIES on Thu, Jun 11 2009

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debug,Functional Verification

How Do You Debug Your Testbench when it Won’t Stand Still?

Verification Goldmine: 50 User Papers on Formal, Multi-Engine, and Assertion-Based Verification (ABV)

Specman-SimVision webinar on April 22 (next week!)

Built-in Message Logging – Part 2 of 2

Tech Tip: Waving Specman Objects in SimVision

Specman 9.2 Preview: Named Constraints

FSM Mnemonics Maps (Enums) in SimVision Using Verilog 1364

Enabling OVM Transaction Debug in SimVision Without Code Changes