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Introduction to Cadence Virtuoso Advanced Node Design Environment
What can designers do about advanced node technology? This is an introduction to the Cadence Virtuoso Advanced Node design environment, announced Jan. 28, 2013, as a custom/analog design development environment for leading edge-advanced node technology. Problems of Advanced Node Design When designing...
Posted to
Custom IC Design
(Weblog)
by
Hiro Ishikawa
on Mon, Jan 28 2013
Whitepaper: New Methodology Needed for 20nm Custom/Analog IC Design
Before digital SoC designers take advantage of the power, performance and density advantages of 20nm, custom/analog designers must develop the standard cells and the analog/mixed-signal IP. Thus, no 20nm solution is complete without an integrated custom/analog capability. A newly published Cadence whitepaper...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Nov 13 2012
Cadence and IBM Outline 20nm Custom/Analog EDA Flow Requirements
No 20nm IC design "solution" is complete without a custom/analog flow that can develop standard cells and analog/mixed-signal IP blocks. That custom/analog flow requires some changes to keep up with 20nm challenges such as double patterning and layout-dependent effects (LDE). A good overview...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 9 2012
On-Line Presentation: 20nm Design Challenges, and a Look Ahead to 14nm
The Common Platform Technology Forum held March 14 in Santa Clara, California, provided an updated look at process technology, design challenges, and ecosystem collaboration at 28nm and below. Much of the content is available throughout 2012 as part of a Virtual Technology Forum . Following is a report...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 19 2012
Free, On-Demand “Tech on Tour” – Digital, Custom/Analog, and PCB
For some time Cadence has offered EDA360 "Technology on Tour" presentations in various cities. Now Cadence is offering on-line Technology on Tour presentations at your desktop, any time, for free. These technical presentations and demos show how to solve common design challenges, and provide...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Dec 1 2011
User View: Challenges and Solutions for Memory IP Development
Developing memory IP isn't easy - it's repetitive full-custom work that requires verification of many possible configurations. While full automation isn't possible, there are ways in which design tools and methodologies can make the task much easier. A recent conversation with engineers at...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Apr 20 2011
Q&A: Jim Hogan Identifies Custom/Analog Challenges and Solutions
Jim Hogan has been a mover and shaker in the EDA industry since long before the term "EDA" was invented. Today a well-known independent venture capitalist, Hogan previously ran both R&D and marketing for the Cadence Virtuoso product, and he knows the custom/analog world well. He's invested...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Mar 20 2011
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