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  • Panel: Signal Integrity Solutions for High Data Rate Interfaces

    Serial link and DDR memory interfaces are well into Gbits/second territory, making it possible to design a new generation of high-performance devices. But these new interfaces can also greatly increase signal integrity challenges. At an August 28 EDN-hosted webinar panel , experts provided a wealth of...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Sep 4 2012
  • Design Signoff Begins In Implementation

    As an ex-design engineer now working in EDA, I am often privileged to see advanced design methodologies from many of my customers. I would like to reflect on the recent trends that I am seeing around signoff analysis for digital ASIC designs. For the majority of ASIC designs, signoff analysis includes...
    Posted to Digital Implementation (Weblog) by PeteMc on Wed, Jan 6 2010
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