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coverage

Coverage results over the time (RTL)

Is it possible to track the coverage results over the time? For bug detection, it is well accepted that the rate at which bug are detected approximates an exponential decay. That is at beggining is should be easier to detect bug, then it becomes more an more complicate. We can distinguish between easy...

Posted to Functional Verification (Forum) by GiuseppeDG on Fri, Apr 26 2013
IMC Merging Issue of different test case of the same DUT.

Dear All, I'm trying to merge the coverage report of different test case of the same DUT but im getting an error saying. Block coverage not merged - Checksum differs. Data is projected in to the target model. The steps used for generating the coverage are: 1. Used the -coverage all option in the...

Posted to Functional Verification (Forum) by Chetz on Mon, Mar 11 2013
DVCon 2013 Expert Panel: How to Succeed with Verification Planning

While formalized methodologies now exist for many aspects of functional verification, verification planning is still largely an ad-hoc process. Yet verification planning is becoming increasingly important as chips get more complex. At the recent DVCon 2013 conference, a panel of verification experts...

Posted to Industry Insights (Weblog) by rgoering on Tue, Mar 5 2013
IMC Exclusion Problem

Hey all, I am using IMC for my coverage .The problem is the tool automaticaly excludes some block coverage or expressions from the coverage.It shows "Exclusion Rule type : simulation time".Can someone explain what does Exclusion Rule typr mean and how do I remove it so that I can cover all...

Posted to Functional Verification (Forum) by Enginerd on Sun, Feb 10 2013
Tracking regression results with an SQLITE database

Hi , I would like to keep track of the verification status of my project (verilog/systemverilog) coverage and pass/fail status of tests during the life of the project. Ideally I want to create an SQLITE database to keep track of this since SQLITE is stored in a file which can be archived with the project...

Posted to Functional Verification (Forum) by andymont on Tue, Jan 15 2013
ncsim: *E,UNKMOD: unrecognized modifier for the coverage -code command (-database)

I encountered this error when I was trying to collect the code coverage of my design. The nc simulation command line contains" +ncinput+./testbench/sim/ict.tcl". And the contents of the file ict.tcl are as follows. coverage -setup -dut top.tb_top.my_design -testname my_design -workdir . coverage...

Posted to Functional Verification (Forum) by czh32689 on Wed, Jan 9 2013
Cadence Partner Udacity Brings Higher Education to the World

On-line education pioneer Udacity is partnering with Cadence to offer an upcoming free class in functional hardware verification - but Udacity's overall mission is quite a bit broader than that. Says David Evans, vice president of education at Udacity (right): "Our mission is to make high-quality...

Posted to Industry Insights (Weblog) by rgoering on Mon, Nov 26 2012
Recorded Webinar: Using Metric-Driven Verification and Formal Together For Higher Productivity

[Preface: the upcoming " Club Formal " on October 17 here at the Cadence San Jose campus will also touch on this topic - please join us! ] While it's now common knowledge that there are many benefits to using simulation technology within a metric-driven verification (MDV) flow , as it turns...

Posted to Functional Verification (Weblog) by TeamVerify on Wed, Oct 10 2012
The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

In July we released 12 videos of the UVM SystemVerilog Basics series with Chinese audio . Now we are completing the set and releasing the remaining 13 videos. Interface UVC Environment Virtual Sequencer - Sequence Module UVC Scoreboard DUT Functional Coverage Testbench Test Configuration Factory Phases...

Posted to Functional Verification (Weblog) by Axel Scherer on Tue, Sep 4 2012
Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus

Ernie & Duracell "I feel great" - long pause - "I feel great, I feel great". 6 weeks later: "I feel great, I feel great, I feel great" - pause - "I feel great". I hear this sound coming out of my son's room. What is going on in my house? Is there such a...

Posted to Functional Verification (Weblog) by Axel Scherer on Wed, Aug 1 2012

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coverage

Coverage results over the time (RTL)

IMC Merging Issue of different test case of the same DUT.

DVCon 2013 Expert Panel: How to Succeed with Verification Planning

IMC Exclusion Problem

Tracking regression results with an SQLITE database

ncsim: *E,UNKMOD: unrecognized modifier for the coverage -code command (-database)

Cadence Partner Udacity Brings Higher Education to the World

Recorded Webinar: Using Metric-Driven Verification and Formal Together For Higher Productivity

The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus