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  • Convergence error in Transient analysis

    Actually i crated a Memristor Model by using VerilogA code. Then i designed logic gates by using the same with different methodology and i got correct simulated output but when i combined all individual logic gates to make a simple 1 bit adder then i got convergence error. I did simulation for 40n sec...
    Posted to Custom IC Design (Forum) by SAMEERGARG on Sun, Apr 20 2014
  • A CPF User Perspective on IEEE 1801 (UPF) “Methodology Convergence”

    By leveraging Common Power Format (CPF) constructs and removing some older Unified Power Format (UPF) commands, the emerging IEEE 1801-2013 standard (UPF 2.1) will help enable "methodology convergence" with CPF. Kamran Haqqani, principal engineer at Maxim Integrated, will be happy to see this...
    Posted to Industry Insights (Weblog) by rgoering on Mon, May 13 2013
  • Problem in Cadence Virtuoso AC analysis

    Hi all, I am facing an often discussed problem while simulating a differential pair in cadence virtuoso. Though I have biased the transistors through DC (though they are in subthreshold mode), yet when I try do do ac analysis (I follow all regular steps) I get a zero magnitude at output. Ths schematic...
    Posted to Custom IC Design (Forum) by OneNewBoy on Thu, Mar 21 2013
  • Re: Different op amp gains using different spectre analysis

    Thanks for reply, However I am facing a very strange problem in my simulation, please help me with this: I am running a parametric simulation to experiment & get the optimal bias current of Op-Amp . For this I gave a list of "I_bias" as "5u 7u " in the parametric analysis window...
    Posted to RF Design (Forum) by OneNewBoy on Thu, Mar 21 2013
  • New Book: Analog Design and Simulation Using OrCAD Capture and PSpice

    Thousands of engineers worldwide use OrCAD Capture for PCB schematic entry and PSpice for circuit simulation. These popular products, both provided by Cadence, deserve a good "how to" book -- and now they have one. It's titled " Analog Design and Simulation Using OrCAD Capture and...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 20 2013
  • VCO transient analysis : Convergence Issues.

    Hi, I am facing convergence issues while doing transient analysis on a LC MOS cross-coupled oscillator. Figure of the NMOS-only cross-coupled oscillator is attached along. Spectre Version : As suggested by Andrew on this forum , I am doing moderate analysis with integration method : traponly...
    Posted to RF Design (Forum) by rsrk on Tue, Oct 30 2012
  • High frequency quadrature VCO design with good phase noise

    Hello everyone I am a newbie engineer starting my career in RF IC design and working on designing a high frequency VCO (38 GHz) with good phase noise characteristics. I am using Cadence IC6.1.5-64b.500 version and spectre simulator for the schemtic design and simulations. I have to do everything from...
    Posted to Custom IC Design (Forum) by rohan kr on Thu, Mar 29 2012
  • Re: Phase Noise vs frequency graph problem

    Thanks Frank for replying. Yes, I have seen that post-it explains the equation which spectre uses to find the pnoise...but it doesnt help me to get the right graph with negative values of pn. I am doing the pss-pnoise simulation using the following settings: PSS : Harmonic Balance beat freq - 37.93G...
    Posted to Custom IC Design (Forum) by rohan kr on Wed, Mar 28 2012
  • Irregularity during DC Sweep Simulation

    Hi all (or specifically to Andrew), I have noticed a strange irregularity during a DC Sweep simulation scenario and I would like to know if anyone knows what could be wrong. I ran DCOp simulations on a test circuit changing a parameter (the supply voltage, VDD) and got certain results. I used nodeset...
    Posted to Custom IC Design (Forum) by aditeman on Wed, Nov 2 2011
  • Guest Blog: Agile Development Eases Convergence in Silicon Realization

    Agile software development methods result in highly adaptive environments that support incremental development with cross-functional teams. According to Neil Johnson, principal consultant at Cadence partner and design services provider XtremeEDA , agile methods are a natural fit for Silicon Realization...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 30 2011
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