will be under maintenance from Friday, Oct. 3rd at 6pm (PST) thru Sunday, Oct 5th at 11pm (PST). login, registration, community posting and commenting functionalities will be disabled.
Home > Community > Tags > constraints
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *


  • True Stories of Assertion Driven Simulation (ADS) in the Wild

    Ever since Assertion-Driven Simulation (ADS) became available, I have been working with customers to integrate ADS into their standard design and verification flow. Below are some true stories from my direct experience with ADS out in the wilds of Silicon Valley. The very first use mode I helped a customer...
    Posted to Functional Verification (Weblog) by TeamVerify on Tue, Jul 5 2011
  • Why Can’t You Write My Assertions for Me? - Part 3

    My last two posts have dealt with various forms of automatic assertion creation and assertion synthesis. There is little doubt that these approaches have significant value, complementing and even replacing some of the assertions written by design and verification engineers. However, I started out this...
    Posted to Functional Verification (Weblog) by tomacadence on Wed, May 4 2011
  • Why Can’t You Write My Assertions for Me? - Part 2

    In my last post , I described three different types of automatic assertions: those derived from the design, those derived from the design with some assumptions such as naming conventions, and those derived from the design plus supplemental files expressing some aspect of design intent. I finished by...
    Posted to Functional Verification (Weblog) by tomacadence on Mon, Apr 25 2011
  • Why Can’t You Write My Assertions for Me? - Part 1

    As regular readers know from previous posts , I have a lot of background in assertion-based verification (ABV) and how assertions are used in simulation and formal analysis. There has been a lot of growth in the use of both assertions and formal since I was first involved in these technologies in 1999...
    Posted to Functional Verification (Weblog) by tomacadence on Tue, Apr 5 2011
  • converting library footprints from protel to allegro

    Hi All, I have some basic doubt in converting library footprints from protel to allegro. Is it possible to convert ? Moreover am using allegro 15.2ver .In this there is no option to import protel board files. It has only import-->pads & pcad. Please help me with the procedure to do this if its...
    Posted to PCB Design (Forum) by Anonymous on Thu, Nov 25 2010
  • Unique DIFFERENTIAL_PAIR properties on complex hierarchical designs : ConceptHDL

    If I add a DIFFERENTIAL_PAIR property on nets wholly contained within the block on the schematic page. Then I instantiate this block multiple times. Is there a way to have the tool generate unique values for each instance? A simple test try resulted in the property remaining unchanged on one block...
    Posted to PCB Design (Forum) by aredenbaugh on Fri, Sep 24 2010
  • Capture 16.3 Errors

    I'd like to report the following error in the 16.3 Version of Capture or Design Entry CIS: When converting a project from 16.01 to 16.3 Net Properties get mangled. I had a design all constrained with Propagation Delays and Relative Propagation Delays placed on a set of high-speed signal groups. When...
    Posted to PCB Design (Forum) by JWWS1 on Wed, Sep 8 2010
  • PCB autorouter(spectraa) not converging

    Hi, I am making my first pcb with a xilinx fpga device(256 pin BGA package).I am simply connecting the all I/O's to 4 standard 40 pin connectors.Are padstacks necessary for PCB routing??.I have drawn the schematic in Capture imported it to Layout_Plus and autorouted it. But after 3 hours of autorouting...
    Posted to PCB Design (Forum) by bennyn1 on Thu, Sep 2 2010
  • Getting Warning X library error detected while trying to open gui for CCD

    I am getting the following warning while trying to switch to the GUI mode in Encounter Conformal Constraint Dessigner(CCD) SETUP> set gui on // Switching to GUI mode X library error detected: 3 - BadWindow (invalid Window parameter) The gui is opening after the warning but it hangs. How can this be...
    Posted to Logic Design (Forum) by rgaddh on Wed, Jun 2 2010
  • Regarding Xnet properties getting lost

    Hi, I am currently using 15.7 Allegro PCB Design XL. I have assigned Models to components to assign XNET properties. Whenever iam importing the latest netlist the Xnet properties are getting lost. Our schematic engineers are using Mentor Dx Designer to generate netlist in .tel format. Every time I import...
    Posted to PCB Design (Forum) by kingshar on Wed, May 26 2010
Page 3 of 4 (36 items) < Previous 1 2 3 4 Next >