Home > Community > Tags > congestion/white paper/routing
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

congestion,white paper,routing

  • New White Paper: Routing Congestion De-Mystified

    Even though routing congestion sounds like a physical design problem, it can cause chip projects to miss schedules, miss performance targets, or result in a larger die size. These are problems that are shared across the project, so if you want to control the success of your chip design project, it is...
    Posted to Logic Design (Weblog) by Jack Erickson on Tue, Jun 16 2009
Page 1 of 1 (1 items)