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common power format

  • Managing Inherited Connections with CPF in Virtuoso
    Let's assume you are managing a schematic-driven top level design in Virtuoso and you want to import a digital block Verilog netlist into Virtuoso. This is a very common use model in mixed-signal implementation. While the Layout Database is saved in Open Access (OA), the optimized Verilog netlist...
    Posted to Mixed-Signal Design (Weblog) by AndreasLenz on Wed, May 23 2012

  • Low-Power Design? Brian Bailey Gets It
    Hats off to Brian Bailey! If you haven't been following his EDA Designline Power Series on eetimes.com you have been missing out. Throughout April, he's been running a pretty comprehensive series of editorials, opinion pieces and contributed articles on the subject of low power design. As he...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, May 2 2012

  • Cadence Customers to Showcase Advanced Low-Power Designs at CDNLive!
    CDNLive! Silicon Valley, taking place at the DoubleTree Hotel in San Jose, CA next week from March 13-14, 2012, brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, Mar 7 2012

  • Si2 Interoperability Guide V2.0 Available for Download

    Recently, the Silicon Integration Initiative (Si2) announced the availability of the Interoperability Guide for Power Format Standards V2.0 . This is an important milestone of power format interoperability between IEEE 1801-2009 and the Common Power Format (CPF). This update was triggered by the Si2's...
    Posted to Low Power (Weblog) by QiWang on Mon, Oct 31 2011

  • Cadence Low Power Guru Wins Si2’s Distinguished Service Award

    Normal 0 false false false EN-US X-NONE X-NONE MicrosoftInternetExplorer4 /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:"";...
    Posted to Low Power (Weblog) by Pete Hardee on Fri, Oct 21 2011

  • Another Expert’s View on Power Intent and Hierarchy
    Normal 0 false false false EN-US X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, Sep 21 2011

  • An Expert’s View on Power Formats and Methodology
    In the last five years since the introduction of power formats, using a side file to describe power intent such as power domains, power modes and associated interface logic has become the mainstream low power design methodology. This marks great progress toward automating complex low power design techniques...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, Aug 24 2011

  • 8 Users Compare RTL Compiler (RC) vs. Design Compiler (DC) on DeepChip.com
    It was refreshing to see what happened when John Cooley made his latest request for reader feedback on his popular DeepChip website catering to the semiconductor design community. A request had come in from a previous DeepChip post prior to the Design Automation Conference (DAC) as follows: Are there...
    Posted to Logic Design (Weblog) by David Stratman on Mon, Jun 20 2011

  • Low Power Design -- Alive and Well at DAC
    Low power design was undoubtedly one of the themes of DAC this year -- especially at the Cadence booth. We drew lively interest on the DAC floor with our low power demo station, which was continuously busy especially on the free Monday. We were showing a new demo explaining how advanced low power techniques...
    Posted to Low Power (Weblog) by Pete Hardee on Tue, Jun 14 2011

  • GUC User Presentation at DAC: How to Do Low Power Design
    Power was clearly a hot topic at the recent Design Automation Conference (DAC). Many companies demonstrated their unique tool capabilities to address power issues at different abstraction levels. However, we saw very few presentations that offered a user perspective on how they do low power designs and...
    Posted to Low Power (Weblog) by QiWang on Mon, Jun 13 2011
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