Home > Community > Tags > clockDesign
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

clockDesign

  • non-clock tree cells on clock tree paths

    Hello, I have a question regarding the use of non-clock tree cells on clock tree paths. The netlist post-synthesis that I have, contains standard muxes and gating-elements on clock paths. During the P&R clock-tree-synthesis step, clock tree buffers are inserted but the standard muxes and gating elements...
    Posted to Digital Implementation (Forum) by chris06 on Fri, Jun 13 2014
  • Is there a way to use CTS with differential (diffpair) clocks?

    Hi, I am researching an implementation idea to use Clock Tree Synthesis (CTS) to route a clock tree that consists of a differential clock. The desired results would be a clock tree that is routed as a diff pair, with differential / matched buffering throughout. Thanks.
    Posted to Digital Implementation (Forum) by TomLM on Fri, Jul 12 2013
  • Unbuffered Clock Tree

    Hello everyone, Does anyone knows how to constraint Encounter to construct Unbuffered Clock Tree? The reason that I am interested in the unbuffered one is because that I am focusing on the sub-vt CTS construction and I have read some papers refer to the unbuffered clock tree. Thanks in advance! Yuqi
    Posted to Digital Implementation (Forum) by Yuqi on Thu, Apr 18 2013
  • Virtual Clock and Synthesize :)

    Hi everyone, I have couple of doubts. Please help me out. 1. My project is about SRAM design controller. While doing compilation i can able to see(in GUI) all my modules in my design but when i synthesize it one of the sub-module(Adress Decoder-FSM module) is not available. What will be the reason for...
    Posted to Digital Implementation (Forum) by Ram S on Sat, Mar 16 2013
  • Manual CTS report

    Hi everyone, I am currently doing a project mainly focus on clock tree synthesis in Cadence Soc Encounter. As I need to study different topology of clock trees, I am using the manual mode CTS. What I have done is: 1.use specifyClockTree command to read in the ctstch file 2.use ckSynthesis command to...
    Posted to Digital Implementation (Forum) by Yuqi on Wed, Feb 6 2013
  • Clock Target Min Latency

    While performing clockDesign, By providing minDelay and maxDelay in clock constraints, Encounter takes MaxDelay as provided in maxDelay target, but it takes MinDelay as '0' even if minDelay is provided. Is their any alternative way to provide Target MinDelay while building Clock Tree, which tool...
    Posted to Digital Implementation (Forum) by RONAKLAD on Thu, Jan 17 2013
Page 1 of 1 (6 items)