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  • Re: Does clock power included in Power Report ?

    [quote user="grasshopper"] Hi dkhan, unfortunately the answer is "It depends" If you are using a netlist and also annotating all parasitics, you will effectively have the clock tree accounted for but if you do not annotate parasitics or working at RTL level, the answer is mostly not...
    Posted to Logic Design (Forum) by dkhan on Mon, Jul 29 2013
  • Does clock power included in Power Report ?

    Hi All, I am conserned whether my power reports include clock power or I have to calculate it separately. Currently I am defining clock period using "define_clock" command before loading my Netlist and then using "report power" command, however when RC loads the VCD file it shows...
    Posted to Logic Design (Forum) by dkhan on Sat, Jul 27 2013
  • How to avoid unwanted removal of logic during synthesis

    Hi All, I am synthesizing a processor design with RTL compiler. The synthesized netlist works fine and contains all necessary logic when I set a loose clock constraint (5000ps). But when I synthesized the same files with a tighter clock constraint (1800- 3000ps) the RTL compiler meets the constraint...
    Posted to Logic Design (Forum) by dkhan on Sun, Jul 7 2013
  • Glitch(Spike) in the output..

    Hello..I am new to cadence, I was trying to simulate the simple 'd' latch using cadence, but i noticed that there is a spike in the output going above my supply voltage and below the ground level( i have rise and fall time of clock and D input as 5 ns). When i increase the rise time and fall...
    Posted to Custom IC Design (Forum) by Raki87 on Sun, Oct 28 2012
  • RC: clock gating

    Hello, What is the right way to insert clock gating in RC script? I found the following flag: set_attribute lp_insert_clock_gating true Is it enough or there is something else needed? How should I translate the following instructions from DC for RC: set_clock_gating_style -sequential_cell latch \ -control_point...
    Posted to Logic Design (Forum) by Yemelya on Wed, Jun 29 2011
  • CtoS support of Multiple Clocks

    In a previous blog entry we discussed C-to-Silicon’s (CtoS’s) ability to support multiple threads in a similar way that traditional Hardware Description Languages (HDLs) support multiple processes. There are many applications, such as multi-rate DSP applications, in which it is not only necessary...
    Posted to System Design and Verification (Weblog) by TeamESL on Mon, Apr 20 2009
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