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clock,VHDL

  • Re: Does clock power included in Power Report ?

    [quote user="grasshopper"] Hi dkhan, unfortunately the answer is "It depends" If you are using a netlist and also annotating all parasitics, you will effectively have the clock tree accounted for but if you do not annotate parasitics or working at RTL level, the answer is mostly not...
    Posted to Logic Design (Forum) by dkhan on Mon, Jul 29 2013
  • Does clock power included in Power Report ?

    Hi All, I am conserned whether my power reports include clock power or I have to calculate it separately. Currently I am defining clock period using "define_clock" command before loading my Netlist and then using "report power" command, however when RC loads the VCD file it shows...
    Posted to Logic Design (Forum) by dkhan on Sat, Jul 27 2013
  • How to avoid unwanted removal of logic during synthesis

    Hi All, I am synthesizing a processor design with RTL compiler. The synthesized netlist works fine and contains all necessary logic when I set a loose clock constraint (5000ps). But when I synthesized the same files with a tighter clock constraint (1800- 3000ps) the RTL compiler meets the constraint...
    Posted to Logic Design (Forum) by dkhan on Sun, Jul 7 2013
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