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clock gating

  • clock tree synthesis for clock gating
    I use clock gating in my design, but it seems the clock tree synthesis only balances the clock to the clock gating cell but not to the leaf register. I have checked the post-layout simulation results. The clock signals to the gating cell are well aligned. But the gated clock signals to the leaf register...
    Posted to Digital Implementation (Forum) by quiet on Wed, Feb 27 2013

  • C-to-Silicon 12.2 Available for Your Holiday Shopping List
    The winter holiday season is that special time of year when we get bombarded with catalogs, emails, television commercials, banner ads, store displays, and any other method to get our attention on something that somebody is trying to sell. Having been trained as an engineer, I'm able to filter a...
    Posted to System Design and Verification (Weblog) by Jack Erickson on Thu, Dec 13 2012

  • how to fix post route clock gating setup violations.
    Hi, I am getting 14 clockgating setup violations(of the order of 300ps) after post route optimization and in ETS timing reports. What is the best way to fix them. Optimization, placement, CTS, etc were done clockGate aware. I was not getting the clockgating violations after post cts stage. Regards Ajesh
    Posted to Digital Implementation (Forum) by ajeshar on Mon, Jun 11 2012

  • Re: Clock Gating as a generated clock in SDC file
    Thanks, I appreciate the input. Can you explain more? these are obviously different commands and perform different tasks, so i don't quite understand how one may justify the absence of another in this case. Unless I use create_generated_clock command, I wonder if the EDA tool will know the shape...
    Posted to Digital Implementation (Forum) by alexsieh on Thu, May 3 2012

  • Clock Gating as a generated clock in SDC file
    Hello, When there is clock gating logic, do I have to define the gated clock as a generated clock in my constraint file for a proper STA? I don't know if anybody is familiar with this great book, but my question came up because I saw an example in the book "Static Timing Analysis for Nanometer...
    Posted to Digital Implementation (Forum) by alexsieh on Wed, May 2 2012

  • Don’t Blow Up Your Chip on the Tester!
    The photo at right shows a test socket and chip destroyed by thermal runaway. Can this really happen? Yes, it can and it sometimes does, if test power is significantly greater than functional power. To get a handle on this problem I talked to Bassilios Petrakis, product marketing director for Design...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 26 2012

  • Clock Gating: Pre or Post Control
    Hi, I am currently using lp_clock_gating_control_point set to postcontrol, simply because this was set in the the scripts I inherited. Are there any signficant advantages of postcontrol over precontrol? I guess that postcontrol has a slight timing advantage, since precontrol has an additonal gate in...
    Posted to Logic Design (Forum) by moogyd on Fri, Feb 11 2011

  • Attention RTL Compiler Customers! RC 9.1.200 Is Here
    Cadence's synthesis R&D team has an early holiday gift for our RTL Compiler customers. The 9.1.200 release (or as our release management system affectionally calls it, "RC9.1-s203") is now available for download. This release is mainly focused on improvements to the core synthesis engine...
    Posted to Logic Design (Weblog) by Jack Erickson on Tue, Dec 15 2009

  • How do I connect an instiantiated library clock gating cell to scan chains?
    In our design, we instantiate a library clock gating cell ("DLSG1") to do functional clock gating at the RTL level. This cell has an SE input which is left unconnected in the RTL code since no other DFT signals are present at this stage: module my_cg ( input clk, input enable, output clk_gated...
    Posted to Logic Design (Forum) by maxb on Tue, Aug 25 2009

  • clock gating paths
    Hi All, In my design i got many clock gating setup violations which are due to negative skew i.e., my launch clock delay is more than capture clock delays.Placement in the design is clock gate aware. Can someone suggest some techniques for these kind of violations.
    Posted to Digital Implementation (Forum) by maven7783 on Mon, Feb 9 2009
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