Home > Community > Tags > chip estimate/TLM
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

chip estimate,TLM

  • ISQED Keynote: Putting Some Numbers To Cost-Aware Design

    We've all heard about the escalating costs of system-on-chip (SoC) development. But what are the costs, and what are the potential savings? Steve Glaser, corporate vice president of strategic development at Cadence, filled in some of those numbers at a keynote speech March 24 at the International...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 29 2010
  • ESL And Silicon IP -- Two Sides Of The Same Coin

    ESL and silicon IP are regarded as two different topics, but in reality they are closely intertwined. This occurs in two significant ways. First, the availability and interoperability of transaction-level modeling (TLM) IP will be a crucial enabler of ESL-based flows. Secondly, IP reuse is perhaps the...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 27 2009
Page 1 of 1 (2 items)