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chip planning

System-Level Low Power Design – What Will it Take to Move There?

While many low-power design techniques are available to IC designers, the greatest potential for power savings is at the system level, where both software and hardware can be considered. So what's standing in the way of system-level low power design, and what needs to happen to make it practical...

Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 18 2012
Q&A: Adam Traidman Updates Silicon IP Trends and ChipEstimate.com

As president and CEO of Chip Estimate before its 2008 acquisition by Cadence, Adam Traidman has been a front-row observer of the silicon IP business for many years. His company developed the InCyte chip planning tool, which includes an IP database to help designers predict area and performance. Today...

Posted to Industry Insights (Weblog) by rgoering on Thu, Feb 23 2012
Friday Fun: InCyte Chip Estimator infomercial

This is our second (and last, for now) foray into the genre of cheesy American commercial advertisement. Here was our first attempt . I've been fascinated with the infomercial approach ever since I received "The ShamWow" for Father's Day from my proud son, who then asked for some red...

Posted to Logic Design (Weblog) by Jack Erickson on Fri, May 14 2010
SoC and remodeling cost estimation

Over at Cadence's Industry Insights blog by Richard Goering , he has a great writeup of a panel at the Virtual SoC Conference entitled "Are SoC Development Costs Significantly Underrated?" In it, there was a great analogy comparing a chip design project to a home remodeling project. This...

Posted to Logic Design (Weblog) by Jack Erickson on Tue, Oct 6 2009
Ah, Power! Now Can I Drive?

Last week a large number of customers and potential customers attended the “System-level Design & Chip Architecture for Low-Power ICs Techtorial and Workshop” sessions in Irvine, San Diego, and San Jose. They must have been monitoring sub-space communication channels or read this blog...

Posted to Logic Design (Weblog) by Mike Carrell on Fri, Apr 24 2009
Friday Fun: Even a Marketing Guy Can Use InCyte!

In this week's episode, Gronk, the unfrozen caveman marketing guy, discovers how easy it is to explore a new power architecture and get both technical and economic estimates using the InCyte software. Meanwhile, the design team realizes that what they need is an Extreme Makeover, Methodology Edition...

Posted to Logic Design (Weblog) by Jack Erickson on Fri, Apr 24 2009
Friday Fun: Caveman Finds Cadence

For those of you new to this series that want to come up to speed quickly, the best bet is to check out the "Notes" for each episode over on the "The Next Generation" Facebook page . Become a fan! After last week's desparation move by Charlene, the team realizes they need to do...

Posted to Logic Design (Weblog) by Jack Erickson on Fri, Apr 10 2009
Can’t Wait To Try Power Management in the New InCyte Release?

Coming up next week are several techtorial events, called " System-level Design & Chip Architecture for Low-Power ICs Techtorial and Workshop ". Yes, that's a keyboard-full of words. But the concept is simple. The main focus is on Power – from system-level to chip architecture...

Posted to Logic Design (Weblog) by Mike Carrell on Fri, Apr 3 2009
New InCyte v3.5 Let’s You Manage Power, Without Being the “Power Expert”

Quantify the trade-offs of Power Management techniques in Early Chip Planning with the new v3.5 release of Chip Planning Solutions . The Chip Planning Solutions team, who comes to Cadence via acquisition of ChipEstimate.com about one year ago, has just released a new version of InCyte . You may be familiar...

Posted to Logic Design (Weblog) by Mike Carrell on Fri, Apr 3 2009
Friday Fun: More Episodes of The Next Generation

Last week we debuted the first two episodes of our creative outlet, "The Next Generation". You could see that clearly not a lot of dollars (zero, to be exact) or time (a few hours) was spent on these. This week's installments are a bit more entertaining (special effects!), and informative...

Posted to Logic Design (Weblog) by Jack Erickson on Fri, Mar 20 2009

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chip planning

System-Level Low Power Design – What Will it Take to Move There?

Q&A: Adam Traidman Updates Silicon IP Trends and ChipEstimate.com

Friday Fun: InCyte Chip Estimator infomercial

SoC and remodeling cost estimation

Ah, Power! Now Can I Drive?

Friday Fun: Even a Marketing Guy Can Use InCyte!

Friday Fun: Caveman Finds Cadence

Can’t Wait To Try Power Management in the New InCyte Release?

New InCyte v3.5 Let’s You Manage Power, Without Being the “Power Expert”

Friday Fun: More Episodes of The Next Generation