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chip estimate

  • Q&A: Adam Traidman Updates Silicon IP Trends and ChipEstimate.com
    As president and CEO of Chip Estimate before its 2008 acquisition by Cadence, Adam Traidman has been a front-row observer of the silicon IP business for many years. His company developed the InCyte chip planning tool, which includes an IP database to help designers predict area and performance. Today...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Feb 23 2012

  • IP Insider Blog: Why Semiconductor IP is Not Dull
    Something interesting has been happening at the Cadence ChipEstimate.com site . Go there and you'll find IP Insider , a new blog written by longtime electronics industry editor John Blyler (right). This bi-weekly blog offers provocative insights into the technical, legal and business issues behind...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Aug 17 2011

  • Friday Fun: InCyte Chip Estimator infomercial
    This is our second (and last, for now) foray into the genre of cheesy American commercial advertisement. Here was our first attempt . I've been fascinated with the infomercial approach ever since I received "The ShamWow" for Father's Day from my proud son, who then asked for some red...
    Posted to Logic Design (Weblog) by Jack Erickson on Fri, May 14 2010

  • ISQED Keynote: Putting Some Numbers To Cost-Aware Design
    We've all heard about the escalating costs of system-on-chip (SoC) development. But what are the costs, and what are the potential savings? Steve Glaser, corporate vice president of strategic development at Cadence, filled in some of those numbers at a keynote speech March 24 at the International...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 29 2010

  • A Critical Step In The IC Design Flow
    Every IC design team does it. Most don’t have a name for it and most don’t use automated tools. It may not show up on flowcharts depicting the IC design flow, and most EDA vendors pay little attention to it. But it’s an absolutely critical part of the IC design flow that can make the...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 14 2010

  • Q&A: Michał Siwiński Sees Major Shift in Product Design and Verification
    The rising costs of product development are causing fundamental changes in the design and verification flows, according to Michał Siwiński, group director of front-end product management at Cadence. In this interview he discusses customer challenges and Cadence strategies in such areas as hardware/software...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 6 2010

  • SoC and remodeling cost estimation
    Over at Cadence's Industry Insights blog by Richard Goering , he has a great writeup of a panel at the Virtual SoC Conference entitled "Are SoC Development Costs Significantly Underrated?" In it, there was a great analogy comparing a chip design project to a home remodeling project. This...
    Posted to Logic Design (Weblog) by Jack Erickson on Tue, Oct 6 2009

  • Cadence’s Xuropa Experience – A New Approach To IP Evaluation
    Evaluating EDA software or silicon IP is an arduous process that often requires negotiated license agreements, software downloads, installation, and the physical presence of a jet-lagged AE who just flew across the country. What if you could run an evaluation instantly on line, and skip all that? That’s...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 30 2009

  • ESL And Silicon IP -- Two Sides Of The Same Coin
    ESL and silicon IP are regarded as two different topics, but in reality they are closely intertwined. This occurs in two significant ways. First, the availability and interoperability of transaction-level modeling (TLM) IP will be a crucial enabler of ESL-based flows. Secondly, IP reuse is perhaps the...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 27 2009

  • Ah, Power! Now Can I Drive?
    Last week a large number of customers and potential customers attended the “System-level Design & Chip Architecture for Low-Power ICs Techtorial and Workshop” sessions in Irvine, San Diego, and San Jose. They must have been monitoring sub-space communication channels or read this blog...
    Posted to Logic Design (Weblog) by Mike Carrell on Fri, Apr 24 2009
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