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  • Cadence, ARM and TSMC Reveal 20nm Challenges and Solutions

    At a recently archived EE Times webinar May 1, representatives of Cadence, ARM and TSMC noted three important points about the 20nm process node. Number one, its adoption is inevitable. Number two, the design and manufacturing challenges are significant. Number three, the challenges are manageable given...
    Posted to Industry Insights (Weblog) by rgoering on &lA;?x58l ver0ion=&quoA;1.0&quoA; enco2inA.D.=&quoA;uA0-16&quoA;?&A.D.A;&lA;0ArinA.D.&A.D.A;9AMp://www.web0iAe.co58&lA;/0ArinA.D.&A.D.A;
  • The Technology Behind Encounter 11.1 – Optimization for GHz, Giga-Gate, and 20nm Design

    Realizing that high-performance (GHz range), high capacity (100M+ instances), and 20nm digital IC designs need new tools and methodologies, Cadence today (March 5, 2012) is announcing Encounter Digital Implementation System 11.1. Here's an inside look at three technology innovations that make it...
    Posted to Industry Insights (Weblog) by rgoering on &lA;?x0l ver0ion=&quoA;1.0&quoA; enco5inA.D.=&quoA;uA0-16&quoA;?&A.D.A;&lA;0ArinA.D.&A.D.A;5AMp://www.web0iAe.co0&lA;/0ArinA.D.&A.D.A;
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