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  • Back annotate / Netlist Update

    I'm new to Orcad so bear with me. I've been using Orcad 16.2 Capture and Layout. The schematic was created in capture and then the board was laid out. In the board, I changed some parts (both name and footprint) as well as some netlists. How do I update the schematic to reflect this? I tried...
    Posted to PCB Design (Forum) by nicknails on Fri, Aug 17 2012
  • Free Tutorial Videos (OrCAD and Allegro)

    Wouldn't it be great if there were a stack of 2 minute long videos, created by product experts, offering free point tutorials on all aspects of PCB and schematic design with Cadence PCB Editor (OrCAD and Allegro)? Well wait no more! http://www.youtube.com/user/parsysEDA/videos?query=how-to can't...
    Posted to PCB Design (Forum) by PCBguru on Tue, Jul 31 2012
  • Capture Netlist Error

    Hi all, I'm new to orcad capture. I designed a small circuit and tried to generate a netlist using PCB editor option, but i got an erroras shown below. Configuration File: C:\Cadence\SPB_16.5\tools\capture\allegro.cfg Spawning... "C:\Cadence\SPB_16.5\tools\capture\pstswp.exe" -pst -d "e...
    Posted to PCB Design (Forum) by LALITH on Tue, Jul 24 2012
  • dsn-files

    Hello everyone, can someone me show the structure of dsn-files or a place I can find them? The background is the following: I' ve build a project in Capture and then created a netlist. But on this procedure something seems to be going wrong. I could'nt load the original dsn-file nor the dbk-file...
    Posted to Logic Design (Forum) by wschira on Sat, Jul 14 2012
  • Re: Capture complains design is opened read only when it is not

    Allan, you are absolutely correct! This problem has plagued me for a year, ever since I discovered the extended preferences menu (which is a difficult enough task and the reason why few people report this problem). It is still a problem in OrCAD version 16.5. And your solution works! NEVER uncheck the...
    Posted to PCB Design (Forum) by SGScreen1 on Wed, Jul 11 2012
  • Design Entry CIS to Design Entry HDL

    Hi! Is it possible to convert all symbols created in CIS into HDL? How? Thanks.
    Posted to PCB Design (Forum) by maberu on Tue, Jul 10 2012
  • What's Good About Capture’s CIS INI Settings? Look to SPB16.5 and See!

    This week, I'm providing a very short blog. While the content is brief and simple, the positive impact to the Allegro Design Entry CIS usability is high! The Capture INI (project level) settings are always dynamic, the CIS settings are more or less static and usually do not change after the initial...
    Posted to PCB Design (Weblog) by Jerry GenPart on Fri, Jul 6 2012
  • Capture CIS prompt:Please enter no more than 31 characters

    Hello there,I'm newer about this forum. My question is that it warned "Please enter no more than 31 characters" when I create a new schematic page and renamed a long charater string more than 31 characters in Capture CIS.However,the number of character of page name could not be less than...
    Posted to PCB Design (Forum) by WhiteSnow on Thu, Jul 5 2012
  • What's Good About OrCAD Capture’s Find Result Report? Look to SPB16.5 and See!

    The OrCAD Capture 16.5 release now has a method to generate a report (in CSV or HTML format) for the results from the Find command. Read on for more details… After you execute the Find command on a design, you can generate a report (in CSV or HTML format) for the results from the Find command...
    Posted to PCB Design (Weblog) by Jerry GenPart on Mon, Apr 23 2012
  • Capturing time

    Hello, I was interested to know if Cadence can keep track of time spent during creation or editing? For example, time spent creating a symbol or a footprint. As we know, some can be quite involved and time consuming but others are very small and straight forward. It would be helpful to know how much...
    Posted to Feedback, Suggestions, and Questions (Forum) by Hotcomb on Fri, Apr 20 2012
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