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cadence

substrate noise analysis

Hi All, I am designing a switching amplifier using a CMOS 65nm process with a normal QFN package. So the noise induced by the switching output stage is quite large. The power supplies are separated for analog and power parts. But the noise can still get through by substrate. I want to find out what is...

Posted to Custom IC Design (Forum) by whlinfei on Wed, May 23 2012
Cadence and IBM Outline 20nm Custom/Analog EDA Flow Requirements

No 20nm IC design "solution" is complete without a custom/analog flow that can develop standard cells and analog/mixed-signal IP blocks. That custom/analog flow requires some changes to keep up with 20nm challenges such as double patterning and layout-dependent effects (LDE). A good overview...

Posted to Industry Insights (Weblog) by rgoering on Wed, May 9 2012
Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology

In a recently archived May 2 webinar , speakers from Cadence and Samsung described a 20nm digital design methodology that can manage challenges such as double patterning, variability, and complexity. The webinar discussed EDA tools, physical IP, and 20nm process technologies, and it highlighted a "proof...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 7 2012
Cadence, ARM and TSMC Reveal 20nm Challenges and Solutions

At a recently archived EE Times webinar May 1, representatives of Cadence, ARM and TSMC noted three important points about the 20nm process node. Number one, its adoption is inevitable. Number two, the design and manufacturing challenges are significant. Number three, the challenges are manageable given...

Posted to Industry Insights (Weblog) by rgoering on Wed, May 2 2012
How TripleCheck IP Validator Eases Use of Verification IP (VIP)

Reusable, commercial verification IP (VIP) has greatly eased the functional verification task for complex interface protocols. However, verification engineers still have a significant amount of manual work to perform. Cadence this week is addressing this problem by announcing the TripleCheck IP Validator...

Posted to Industry Insights (Weblog) by rgoering on Mon, Apr 30 2012
Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification

Seven years ago this month (April 2005) Cadence acquired Verisity, the pioneering verification company that developed the e language and the Specman environment. The acquisition resulted in a paradigm shift in IC verification, setting the stage for reusable verification methodologies, constrained-random...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 24 2012
IPC-2581 Update: Forward Progress on a PCB Data Transfer Standard

Six months ago, I wrote about a lively panel discussion at PCB West about printed circuit board data transfer standards. Most panelists - and many audience members - were supportive of IPC-2581, an "intelligent" data format that can potentially replace the various formats that designers use...

Posted to Industry Insights (Weblog) by rgoering on Mon, Apr 23 2012
Free Webinars Preview 20nm Challenges, Solutions

If you're designing or planning to design at 20nm - or you're just curious about this emerging and much-discussed process node - three free webinars May 1, 2 and 3 will provide a wealth of valuable information. In these webinars, Cadence experts will team up with industry leaders to present 20nm...

Posted to Industry Insights (Weblog) by rgoering on Thu, Apr 12 2012
Panelists: What Needs to Happen for 3D-IC TSV Success

It's time to get to work if we want to bring 3D-ICs with through-silicon vias (TSVs) into the semiconductor design mainstream. What ecosystem support is needed in the short term, medium term, and long term to make this new technology successful? That's the question that was put to a panel of...

Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 11 2012
EDA Symposium: How Wide I/O is Driving 3D-ICs with TSVs

Any new technology needs a driving force or "killer app," and 3D-ICs with through-silicon vias (TSVs) are no exception. By allowing a high-bandwidth, low-power connection between CPU and DRAM, the new JEDEC wide I/O mobile DRAM standard will be that driving force, according to Marc Greenberg...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 10 2012

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cadence

substrate noise analysis

Cadence and IBM Outline 20nm Custom/Analog EDA Flow Requirements

Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology

Cadence, ARM and TSMC Reveal 20nm Challenges and Solutions

How TripleCheck IP Validator Eases Use of Verification IP (VIP)

Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification

IPC-2581 Update: Forward Progress on a PCB Data Transfer Standard

Free Webinars Preview 20nm Challenges, Solutions

Panelists: What Needs to Happen for 3D-IC TSV Success

EDA Symposium: How Wide I/O is Driving 3D-ICs with TSVs