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cadence

Tempus – Parallelized Computation Provides a Breakthrough in Static Timing Analysis

Cadence today (May 20, 2013) is announcing the Tempus Timing Signoff Solution , a new static timing analysis and closure tool that offers significant speed and capacity advantages over existing solutions. Tempus promises to accelerate signoff timing closure by a matter of weeks. One factor behind this...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 20 2013
DAC 2013: “IP Talks!” Shows What’s New in Semiconductor IP

If you're working with semiconductor IP at any phase of the design and verification process, the IP Talks! presentations at the ChipEstimate.com booth at the upcoming Design Automation Conference (DAC 2013) will provide a great deal of useful information. Now in its 7 th year, IP Talks! includes...

Posted to Industry Insights (Weblog) by rgoering on Thu, May 16 2013
DAC 2013: User Perspectives on System-Level Verification

The best way to learn about an emerging technology is to hear from the people who are using it. If you're curious about system-level design and verification, you can do just that at the Cadence System-to-Silicon Verification Breakfast at the Design Automation Conference ( DAC 2013 ) Tuesday, June...

Posted to Industry Insights (Weblog) by rgoering on Wed, May 15 2013
Noise sources in PSS analysis

Hi all, I have a pretty simple doubt. I am using Verilog A based circuit netlist to perform circuit simulation in cadence spectre. I have defined some flicker noise sources in the same netlist. If I simulated a simple differential amplifier, I can get the inut referred noise through noise analysis. Now...

Posted to Custom IC Design (Forum) by OneNewBoy on Tue, May 14 2013
What's Good About AMS Data Precision Options? They’re in the 16.6 Release!

Just a brief blog today to introduce that 16.6 Allegro AMS Simulator (PSpice) now provides 64-bit data precision by default. This ensures a higher precision compared to the 32-bit data. For example, when a very small amplitude voltage is superimposed on a large voltage, the resulting voltage loses its...

Posted to PCB Design (Weblog) by Jerry GenPart on Mon, May 13 2013
how to use "insertXMlMenu" in capture

There is a "insertXMLMenu" function in capture's tcl demo as follow: InsertXMLMenu [list [list "TopLevelMenu"] "" "" [list "popup" "&TopLevelMenu" "0"]] InsertXMLMenu [list [list "TopLevelMenu" "SubMenu"...

Posted to PCB SKILL (Forum) by robin chu on Wed, May 8 2013
Joe Costello at EDAC: “Secrets” for Telling a Compelling Company Story

There is no doubt that Joe Costello, the first Cadence CEO, knows how to tell a compelling company story. Under his charismatic leadership, Cadence experienced explosive growth after its formation in 1988, becoming the largest EDA company within just a few years. It is thus fitting that the EDA Consortium...

Posted to Industry Insights (Weblog) by rgoering on Sun, May 5 2013
Customer Support Recommended - Instance and Occurrence Modes of Design Annotation using OrCAD Capture

Assigning reference designators for the schematic instances is a very vital part of the entire PCB flow. This can sometimes become very cumbersome, and in some cases users allocate a major portion of their time and effort to get the assignments correct and optimized. Annotation is the automated process...

Posted to PCB Design (Weblog) by Naveen on Thu, May 2 2013
Creating Virtual Platform Models

One of the most common questions asked about virtual platforms is: Who creates the models? There are many sources of models and there are people who can make additional models (like Cadence), but obtaining some experience in model creation and virtual platform construction is a great skill to have if...

Posted to System Design and Verification (Weblog) by jasona on Mon, Apr 29 2013
What's Good About ADW’s Design Migration? 16.6 has many new enhancements!

Prior to the Allegro Design Workbench (ADW) 16.6 release, the migration process required multiple executables: – Netassembler – Archiver – Purge – Packager It was also less robust with dependencies on external programs, and the error resolution was not always clear. With the 16...

Posted to PCB Design (Weblog) by Jerry GenPart on Mon, Apr 29 2013

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cadence

Tempus – Parallelized Computation Provides a Breakthrough in Static Timing Analysis

DAC 2013: “IP Talks!” Shows What’s New in Semiconductor IP

DAC 2013: User Perspectives on System-Level Verification

Noise sources in PSS analysis

What's Good About AMS Data Precision Options? They’re in the 16.6 Release!

how to use "insertXMlMenu" in capture

Joe Costello at EDAC: “Secrets” for Telling a Compelling Company Story

Customer Support Recommended - Instance and Occurrence Modes of Design Annotation using OrCAD Capture

Creating Virtual Platform Models

What's Good About ADW’s Design Migration? 16.6 has many new enhancements!