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DAC 2013: User Perspectives on System-Level Verification
The best way to learn about an emerging technology is to hear from the people who are using it. If you're curious about system-level design and verification, you can do just that at the Cadence System-to-Silicon Verification Breakfast at the Design Automation Conference ( DAC 2013 ) Tuesday, June...
Posted to
Industry Insights
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by
rgoering
on Wed, May 15 2013
Martin Lund CDNLive Keynote: Why SoCs Need “Application Optimized” IP
Systems on chip (SoCs) are incredibly varied, extremely complex, and based on rapidly changing requirements and specifications, according to Martin Lund, senior vice president for R&D at the Cadence SoC Realization Group. At a keynote speech at the CDNLive Silicon Valley conference March 12, 2013...
Posted to
Industry Insights
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by
rgoering
on Thu, Mar 14 2013
DVCon 2013 Preview – Learn from Other Design and Verification Engineers
The Design and Verification Conference ( DVCon 2013 ) will be held Feb. 25-28 at the Doubletree Hotel in San Jose, California - and this year's program has something of interest for almost every design and verification engineer. The conference offers 12 technical sessions, 10 tutorials, two panels...
Posted to
Industry Insights
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by
rgoering
on Thu, Jan 24 2013
Webinar Report: Assertion-Based Verification IP Ensures ARM ACE Protocol Compliance
Do you want to enjoy the benefits of formal verification without having to become an expert? A newly archived Cadence webinar shows how you can do just that, using assertion-based verification IP (ABVIP) that supports both formal and dynamic verification of systems-on-chip using the ARM ACE protocol...
Posted to
Industry Insights
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by
rgoering
on Wed, Dec 19 2012
Cadence at ARM TechCon – Verification IP, 14nm FinFET, Low Power, Mixed Signal, and More
With nine technical paper presentations, six sponsored sessions, demos, and exhibits, Cadence will have a strong presence at ARM TechCon in Santa Clara, California Oct. 30-Nov. 1, 2012. Cadence papers and sessions will cover topics including advanced-node digital, mixed-signal, low power, verification...
Posted to
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by
rgoering
on Tue, Oct 23 2012
MemCon Keynote: Cloud, Mobility Disrupt Semiconductor Memory Ecosystem
Do you think memory is a boring, slow-moving technology? That's definitely not the case, according to Martin Lund (right), senior vice president at Cadence and keynote speaker at the MemCon 2012 conference Sept. 18, 2012. Lund asserted that these are "exciting times" for a semiconductor...
Posted to
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by
rgoering
on Tue, Sep 18 2012
Q&A: Cadence VP Martin Lund Brings User Perspective to Semiconductor IP
Martin Lund joined Cadence in early 2012 as senior vice president of R&D for the SoC Realization Group. He hasn't worked for an EDA company in the past, but 12 years at Broadcom -- most recently as senior vice president and general manager of Broadcom's Network Switching Business -- gave...
Posted to
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rgoering
on Mon, Aug 20 2012
DAC 2012: Users Cite Experiences With Hardware/Software Co-Development
Hardware/software co-development tools such as virtual prototyping, emulation, and FPGA-based prototyping are in use today and are making a difference. That was the message behind a Cadence-sponsored breakfast at the Design Automation Conference ( DAC 2012 ) June 5, where two users described their experiences...
Posted to
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by
rgoering
on Sun, Jun 17 2012
How TripleCheck IP Validator Eases Use of Verification IP (VIP)
Reusable, commercial verification IP (VIP) has greatly eased the functional verification task for complex interface protocols. However, verification engineers still have a significant amount of manual work to perform. Cadence this week is addressing this problem by announcing the TripleCheck IP Validator...
Posted to
Industry Insights
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by
rgoering
on Mon, Apr 30 2012
Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification
Seven years ago this month (April 2005) Cadence acquired Verisity, the pioneering verification company that developed the e language and the Specman environment. The acquisition resulted in a paradigm shift in IC verification, setting the stage for reusable verification methodologies, constrained-random...
Posted to
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on Tue, Apr 24 2012
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