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cadence,Incisive
: Functional Verification
ABV
ABVIP
Accelerated Verification IP
Acceleration
ACE
ACE protocol
Adam Sherer
Advanced Profiler
AMD
ARM
ARM ACE
assertion-based simulation
assertion-based verificatioin
assertions
AVIP
Axel Scherer
Chinmay Banerjee
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Coverage-Driven Verification
CS348
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Debug
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Denali
design for test
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Frank Schirrmeister
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Freescale
Functional Verification
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IDA: Functional Verification
IEEE 1647
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DAC 2013: User Perspectives on System-Level Verification
The best way to learn about an emerging technology is to hear from the people who are using it. If you're curious about system-level design and verification, you can do just that at the Cadence System-to-Silicon Verification Breakfast at the Design Automation Conference ( DAC 2013 ) Tuesday, June...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 15 2013
Incisive Debug Analyzer is a Finalist for EETimes and EDN ACE Software Product of the Year
Great news.... Incisive Debug Analyzer (IDA) is one of five finalists for the EETimes/EDN Annual Creativity in Electronics (ACE) Awards in the Software Product of the Year category. In addition to IDA, Lip-Bu Tan and Cadence are also finalists for ACE Executive of the Year and Company of the Year, respectively...
Posted to
Functional Verification
(Weblog)
by
Karnane
on Mon, Mar 25 2013
Launch Time – Udacity CS348 Functional Hardware Verification Hits the Web Today, March 12, 2013
Coinciding with the first day of CDNLive! Silicon Valley, our Udacity MOOCs course on Functional Hardware Verification will go live today! Developing this course has been a very rewarding experience and we are happy this day has finally come. Last week we gave you a sneak preview of the interactivity...
Posted to
Functional Verification
(Weblog)
by
Axel Scherer
on Tue, Mar 12 2013
System to Silicon Verification – CDNLive Gives a Reality Check on How Hardware and Software Meet
Ever since switching from being a hardware/software chip developer to being an enabler with tools in EDA and embedded software, I was part of a team working towards methodologies and tools to improve the interaction of hardware and software. In December last year -- 15 years in -- I summarized a great...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Fri, Mar 8 2013
Whitepaper Review: Improving Gate-Level Simulation Performance
As I wrote in a January 2013 blog post , a recent Cadence customer survey confirmed that gate-level simulation usage is increasing, and that it can potentially take up to one-third of the simulation time and over half the debugging time. Since gate-level simulation is much slower than RTL simulation...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Feb 18 2013
Improve Debug Productivity - SimVision Video Series on YouTube
Most verification customers claim that they are spending over 50% of their verification effort in debug. If so, you should check out these latest SimVision debug videos since you will quickly see how SimVision can enable you to be much more productive in less than an hour after viewing the videos. Take...
Posted to
Functional Verification
(Weblog)
by
Karnane
on Tue, Feb 5 2013
Functional Verification Survey -- Why Gate-Level Simulation is Increasing
In a recent webinar on increasing functional verification performance, the point was made that gate-level simulation usage is increasing. Wait a minute, I thought - haven't we spent the last two decades talking about raising the abstraction level for design and verification? While some IC verification...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 16 2013
Webinar Report: Assertion-Based Verification IP Ensures ARM ACE Protocol Compliance
Do you want to enjoy the benefits of formal verification without having to become an expert? A newly archived Cadence webinar shows how you can do just that, using assertion-based verification IP (ABVIP) that supports both formal and dynamic verification of systems-on-chip using the ARM ACE protocol...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Dec 19 2012
Webinar Report: Speeding RTL and Gate-Level Simulation
Every verification team wants faster functional verification performance. Fortunately, there are many ways to achieve that. A recently archived Cadence webinar illustrates a number of techniques for speeding both RTL and gate-level simulation, including "out of the box" improvements to the...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Dec 13 2012
Q&A: Phil Bishop, New Cadence VP, Drives Adoption of System-Level Design
Phil Bishop has come into his new role - Vice President and General Manager of System Level Design at Cadence - at an exciting time. After years of slow growth, technologies such as high-level synthesis and virtual prototyping are seeing adoption and showing results in more and more production environments...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Oct 8 2012
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