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Q&A: Qi Wang Updates EDA Power Intent Format Standards
IC design teams can use one of two formats to express power intent - the Common Power Format (CPF) from the Silicon Integration Initiative ( Si2 ), or IEEE 1801 , also known as the Unified Power Format (UPF). Efforts are now underway to bring the two formats closer together, and Qi Wang, technical marketing...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 20 2013
DVCon 2013 Preview – Learn from Other Design and Verification Engineers
The Design and Verification Conference ( DVCon 2013 ) will be held Feb. 25-28 at the Doubletree Hotel in San Jose, California - and this year's program has something of interest for almost every design and verification engineer. The conference offers 12 technical sessions, 10 tutorials, two panels...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jan 24 2013
Free UVM Tutorial Boosts IC Functional Verification Skills
Whether you're new to the Universal Verification Methodology (UVM) or an experienced user who wants to know more, a free on-line tutorial will help you improve your IC verification skills. The half-day tutorial, titled " UVM: Ready, Set, Deploy! " is available through the Accellera Systems...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 12 2012
DAC 2012: How Unified Coverage Interoperability Standard (UCIS) Will Ease IC Verification
Some significant news was announced at the Design Automation Conference June 4 - the official debut of the Unified Coverage Interoperability Standard ( UCIS 1.0 ) by the Accellera standards organization. Accellera hosted a June 6 lunch event at which Richard Ho (right), co-chair of the UCIS Committee...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jun 11 2012
Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification
Seven years ago this month (April 2005) Cadence acquired Verisity, the pioneering verification company that developed the e language and the Specman environment. The acquisition resulted in a paradigm shift in IC verification, setting the stage for reusable verification methodologies, constrained-random...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Apr 24 2012
2011 EDA Standards Update and 2012 Forecast
As system complexity grows and semiconductor process nodes shrink, EDA industry standards are more important than ever. With today's time-to-market pressures, the last thing you'd want to do is waste time due to incompatible formats, tools or methodologies. Fortunately, 2011 was a productive...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Dec 21 2011
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