Home > Community > Tags > cadence/ADE
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

cadence,ADE

  • How to characterize Transistors for gm/Id based design.

    Hi, Q1. Can someone give the circuit for characterizing Transistors for gm/Id based design, as I found different circuits in differrent websites. Also what size of W should be taken when generating plots as I am using 180nm Technology. Q2. I am able to plot fT vs gm/Id for single length after going to...
    Posted to Custom IC Design (Forum) by Meraj on Sat, Sep 28 2013
  • How Cadence Helps Universities Build EDA Infrastructures

    Many EDA companies, including Cadence, have university programs that make it easier for academia to acquire tools. But what about the software/hardware infrastructure that supports those tools? In this era of budget shortfalls, university compute infrastructures are under severe stress. Recently the...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Nov 7 2012
  • substrate noise analysis

    Hi All, I am designing a switching amplifier using a CMOS 65nm process with a normal QFN package. So the noise induced by the switching output stage is quite large. The power supplies are separated for analog and power parts. But the noise can still get through by substrate. I want to find out what is...
    Posted to Custom IC Design (Forum) by whlinfei on Wed, May 23 2012
  • ADE hangs up when java is running

    Dear Cadence-Experts, I have a problem with the ADE (Analog Design Environment) running within a newly installed Cadence software (IC 6.1.3, MMSIM 7.01, IUS 8.10 under RedHat 4 on Intel Core i7 CPU 950). Problem scenario 1: * A quick way to trigger the problem is to try to change the "Project Directory"...
    Posted to Custom IC Design (Forum) by Michael2010 on Thu, Nov 25 2010
  • Multiple Model Files

    Hi, I am working on a circuit where I need multiple model files. The first one I am using is gpdk045, I tried modifying this file to use with transistors from the analog library. The problem I have is that my simulations are wrong whenever I use a transistor with the second model file it just produces...
    Posted to Custom IC Design (Forum) by Karo on Wed, Jul 21 2010
  • How to suppress Spectre simulation for digital design?

    I am using Cadence 6.1.2 and NCSU_analog_parts library to do digital design. When I use spectre to simulate my circuit, it costs a long time (40 minutes at least) and a large file generated (more than 15MB). So I'd like to know how to suppress the simulation of Spectre´╝č Because I think it may do...
    Posted to Custom IC Design (Forum) by Shengkui Gao on Thu, Feb 25 2010
  • Problem with Simulating Design using Spectre

    I have created a schematic using Virtuoso 6. When I open the ADE, it says "(deLicense-7) Could not get a license for ADE L. Would you like to try to get a higher-tiered license to run this product?" When I click on Yes, it starts the ADE, but when I set up the analysis and click on "Netlist...
    Posted to Custom IC Design (Forum) by govilv on Thu, Jun 4 2009
  • Display operating point

    Hi, I am using CMOS 90nm technology in cadence and I just wonder how I can display the region of operation, gm, and id etc for my transistors. I tried the same steps that we used to do for cmosp18 technology in cadence but I couldn't succeed. Thanks. -Santosh
    Posted to Custom IC Design (Forum) by santoshvema on Tue, May 5 2009
Page 1 of 1 (8 items)