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cadence 6.1 virtuoso

  • compatibility of Assura 3.1 for 65 nm process
    Hi, I have been using Assura 3.1 for DRC,LVS and extraction for 0.35 um cmos process and now we have been using 65 nm process. Does this Assura is capable for DRC, LVS and including extraction for 65 nm cmos process.
    Posted to Custom IC Design (Forum) by Jithin on Sat, May 25 2013

  • Phase noise plot
    Hi, I have been doing a Pnoise analysis . Unfortunately I was unable to plot the phase noise response. My design was setup was described below. My apparatus was a PLL with a fixed divider ratio of 20 and output frequency of 500Mz In PSS analysis I have set the beat frequency as reference frequency ie...
    Posted to Custom IC Design (Forum) by Jithin on Wed, Apr 10 2013

  • Generating LEF from layout view
    Hi all! I have been trying to export LEF from standard cells layout in order to use that LEF file in Encounter for automatic PnR. From virtuoso I select File -> Export -> LEF and fill the form appropriately but the lefout.log is giving a warning on metal 4 as shown below: Warning (OALEFDEF-50144...
    Posted to Custom IC Design (Forum) by BraveHeart on Tue, Jun 12 2012

  • Running Cadence IC on VMware?
    My IT department is very enthusastic about putting everything on VMware. They say that this will make their job much easier. I would like to know if you, anyone, or your company has tried running Cadence IC, ADE, or Virtuososo (any version) on VMware and how it worked out for you.
    Posted to Custom IC Design (Forum) by John Reeder on Fri, Apr 6 2012

  • Transient noise
    Hi , What does the transient noise tab in the analyses window of spectre means and what were the values should be given for noise max. ,noise min and bins if my oscillator is working at 450MHzand running for 150ns. Thanks in advance. with regards, Jithin
    Posted to Custom IC Design (Forum) by Jithin on Wed, Mar 21 2012

  • Modelling noise in Power supply
    Hi, I'm designing a VCO based on ring oscillator architecture and would like to simulate power supply Jitter using cadence spectre. so please help me in adding noise to power supply or help me in modelling supply with jitter. Thanks in advance. with regards, Jithin
    Posted to Custom IC Design (Forum) by Jithin on Wed, Mar 7 2012

  • Re: How to perform Post-Layout simulations using UltraSim for Black-Box Cells?
    Hi Quek Thanks for your reply. I specified the dpf file as per your advice and the simulation has completed successfully and a graph is also plotted but results are not correct! Actually ultrasim is not able to find the 'INVXL' subcircuit. (which is Artisan's standard cell). Here is the message...
    Posted to Custom IC Design (Forum) by BraveHeart on Wed, Oct 26 2011

  • Cadence crash !
    Hi, I have just installed a new PDK on my CADENCE IC 6.1.4, and I have the following errors that I cannot solve! : 1/ When I launch cadence IC6.1.4 with the command: "virtuoso", I can see in the CIW window that the initialization runs a lot of time and finally ends with : " * Error * unknown...
    Posted to Custom IC Design (Forum) by lraf on Fri, Aug 26 2011

  • Layout of Enclosed Gate Transistors (EGTs or ELTs)
    Hello, I'm designing an enclosed layout transistor but can not pass both DRC and LVS. I'm running IBM's PDK cmrf7sf V1.8.0.6 ML, out of virtuoso rev 6.1.4, and my simulator is Assura. Does anyone have any experience in getting a ELT to pass DRC and LVS in this process? Any help would be greatly...
    Posted to Custom IC Design (Forum) by bnugent on Wed, Jun 15 2011

  • error when launching cadence IC610
    Hi everyone, I just installed IC610 on our Linux machine (radhat enterprise5, 64bit) . We have a IC5141 on it already by the way. I got error when I tried to run the IC610. I put "virtuoso" and error information comes: /cadence/IC610/tools/dfII/32bit/virtuoso: symbol lookup error: /cadence...
    Posted to Custom IC Design (Forum) by Sindy on Sat, Apr 9 2011
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