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bugs

Video: Oski Technology’s Courageous "72 hour Verification Challenge" Using Incisive Enterprise Verifier (IEV)

I've seen a lot of intriguing promotions over the years, but at DAC 2012 our partners at Oski Technology tackled a truly unique challenge. To show off their formal verification prowess they took an IP block from NVIDIA sight unseen (actually, on Sunday evening before the DAC they received a spec...

Posted to Functional Verification (Weblog) by TeamVerify on Mon, Jun 25 2012
Automating UVM to Tackle Insidious HW/SW Bugs

You've just sat through a 2-hour program review. The 30 minutes you spent describing your sparkling new UVM verification environment were electrifying. Of course, the hardware and software reviews were boring. Blah, blah, blah about design trade-offs with some buried references to register APIs....

Posted to Functional Verification (Weblog) by Adam Sherilog on Mon, Oct 10 2011
DVClub Talk: Software-Inspired Technique Predicts IC Verification Closure

What's the hardest question for a verification manager to answer? Greg Smith, senior verification manager at Oracle, found that out soon after he moved from design into verification at Hewlett-Packard some years ago. The question is, "when will you be done?" At a DVClub Silicon Valley meeting...

Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 18 2011
What Could Be Simpler than a Request-Acknowledge Handshake?

My last few blog posts have included three corner-case conditions that led to bugs, one in software, one in hardware, and one in real life. One of the reasons that corner-case conditions are missed is that some engineers don't spend enough time really thinking about their design and documenting its...

Posted to Functional Verification (Weblog) by tomacadence on Mon, Jan 31 2011
How I Nearly Had My Own “Subtract Bug” in a CPU Design

In a recent blog post , I talked about learning a public lesson on the importance of software verification while an intern at Digital Equipment Corporation (DEC). Since I spent most of my early career as a logic designer, not a programmer, I figure that an example of a corner-case condition from that...

Posted to Functional Verification (Weblog) by tomacadence on Tue, Jan 4 2011
Those Corner-Case Conditions Caught You Again!

In my last blog post , I related a story from my engineering past in which I learned the hard way about the value of anticipating and verifying corner-case conditions. That story was technical in nature, having to do with inadequate verification of software. However, sometimes the corner cases we encounter...

Posted to Functional Verification (Weblog) by tomacadence on Wed, Dec 15 2010
How Do You Debug Your Testbench when it Won’t Stand Still?

The task of debugging a simulation problem in your design can be a difficult and time consuming task. These days, the verification engineer must also be able to debug very complex SystemVerilog testbenches too. This becomes difficult because of their dynamic nature -- they just won’t stand still...

Posted to Functional Verification (Weblog) by jimkje on Tue, Dec 14 2010
Corner-Case Conditions Will Get You Every Time

Experienced verification engineers know that most killer bugs lurk deep in the corners of the design, triggering only when certain combinations of conditions occur. Most modern functional verification techniques, from formal analysis to constrained-random stimulus backed by functional coverage, are expressly...

Posted to Functional Verification (Weblog) by tomacadence on Fri, Dec 10 2010

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bugs

Video: Oski Technology’s Courageous "72 hour Verification Challenge" Using Incisive Enterprise Verifier (IEV)

Automating UVM to Tackle Insidious HW/SW Bugs

DVClub Talk: Software-Inspired Technique Predicts IC Verification Closure

What Could Be Simpler than a Request-Acknowledge Handshake?

How I Nearly Had My Own “Subtract Bug” in a CPU Design

Those Corner-Case Conditions Caught You Again!

How Do You Debug Your Testbench when it Won’t Stand Still?

Corner-Case Conditions Will Get You Every Time