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  • Capture NetGroup bug

    Capture 16.5 Accidentally I found sequence to create non-erasable NetGroup 1. Created NetGroup A 2. Create NetGroup B which use A 3. Create NetGroup C which use A as element of bus 4. Delete A from C (actually it is mistake) Now impossible to modify/delete A and all who referred to A become messed up...
    Posted to PCB Design (Forum) by kimstik on Wed, Sep 17 2014
  • Improve Debug Productivity - SimVision Video Series on YouTube

    Most verification customers claim that they are spending over 50% of their verification effort in debug. If so, you should check out these latest SimVision debug videos since you will quickly see how SimVision can enable you to be much more productive in less than an hour after viewing the videos. Take...
    Posted to Functional Verification (Weblog) by Karnane on Tue, Feb 5 2013
  • Re: Slow Network Licence cadence 16.5

    Hi, I have some updates regarding my problem: - it looks like that the problem is the antivir software from avira the only way that i found out to get orcad 16.5 running proper with a fast (t=~ms) license request form the licence server is: - remove and install my system (Win 7) completely...
    Posted to PCB Design (Forum) by blaenks on Thu, Jan 12 2012
  • The Tale of the Silicon Re-Spin and the Bug That Got Away

    I'd like to continue my blog series discussing corner-case conditions of various kinds that I have encountered in my engineering career. So far they've all had happy endings. I discussed a software bug that was only in a prototype, not an actual product, so no real damage was done. I described...
    Posted to Functional Verification (Weblog) by tomacadence on Thu, Feb 17 2011
  • PCB Editor - Tree view not available

    I am very new to PCB Editor and I'm sure I will end up posting a fair amount of Forum questions. The first is that I am trying to do a manual place of components in the PCB Editor, and my tree view doesn't seem to be appearing properly. In all the examples I have seen, there are check boxes next...
    Posted to PCB Design (Forum) by ChrisL2 on Mon, Jan 17 2011
  • Disappearing geometry

    I have a pCell where contacts are repeated as the width increases - pitch = 12 .0 repeats = (wu + 4.0)/12.0 This works as expected for all widths EXCEPT the default, minimum, width in the CDF which is 8.0. When "wu" is 8.0, the contact disappears. If I make the CDF default 7.0 then the contact...
    Posted to Custom IC Design (Forum) by Dean1138 on Thu, Mar 4 2010
  • Paths Merge bug

    Hi all, I know that this is not correct forum to describe this bug, but if you know right address please send it to me. The problem happens with Cadence icfb ver. 1) creat metal path with L shape ( |__ ) 2) copy it with horizontal shifting (to have two overlapped L shape: |__|__) 3...
    Posted to Custom IC Design (Forum) by marcop on Mon, May 25 2009
  • Error in Virtuoso..

    Hi all.. I got this error while designing, I have never encountered it before. Can anyone help me ? Loading /opt/cadence/IC5141/tools.lnx86/cmi/lib/4.0/libinfineon_sh.so ... Loading /opt/cadence/IC5141/tools.lnx86/cmi/lib/4.0/libnortel_sh.so ... Loading /opt/cadence/IC5141/tools.lnx86/cmi/lib/4.0/libphilips_sh...
    Posted to Custom IC Design (Forum) by kgulur on Sat, Sep 27 2008
  • Virtuoso ADE bug: netlist regenerated even when clicking yellow light

    Whenever I click the yellow light (the run button) and NOT the green light (netlist and run), a new netlist is generated anyway. Is this a bug? Is there some setting that I should change to stop this from happening? Thanks, Daisy
    Posted to Custom IC Design (Forum) by Heartilly2000 on Tue, Aug 12 2008
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