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broadcom
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User View: Broadcom Evaluates Clock Concurrent Optimization (CCOpt)
Clock concurrent optimization (CCOpt) is a new technology that runs clock tree synthesis (CTS) concurrently with physical optimization. It claims significant improvements in performance, power, and area - but the only way to really quantify such claims is through customer experience with real designs...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 23 2012
DVCon User Panelists: Is Low Power Design Worth the Costs?
Much has been written about the specific techniques that IC designers can use for low-power design and verification, but a larger context is missing. What's the end goal, and what are the costs, benefits, and challenges of implementing power management? In a lively panel discussion at the DVCon conference...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 29 2012
Free “Power” Lunch at DVCon Exposes Verification Challenges
A free lunch, a 50% off deal on a new verification book, and a chance to hear about real-world experiences in low-power verification -- it's all happening Tuesday Feb. 28 at the DVCon 2012 conference in San Jose, California. The Cadence-sponsored lunch, which runs from 12:30 pm to 2:00 pm, is titled...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 22 2012
ARM TechCon Address: High Stakes at Low Process Nodes
The complexity of advanced-node IC designs is skyrocketing, and the demands on EDA tool development seem overwhelming - but innovation and deep collaboration will break through the challenges, according to Chi-Ping Hsu, senior vice president for R&D at the Silicon Realization group at Cadence. In...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Oct 25 2011
User View: How Formal Techniques Verify Memory Wrappers
Broadcom uses a lot of memory in its video processing ICs, and that causes a simulation bottleneck, according to Normando Montecillo, senior principal engineer at Broadcom. But the company has found a better way - using formal verification and assertions to develop a new flow for verifying memory wrappers...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jul 27 2011
Video: DVCon and DVClub Case Study: NextOp’s BugScope for Assertion-Based Verification (ABV)
Attendees of the Silicon Valley DVClub this past Tuesday were treated to some real life case studies of new tools that help D&V engineers rapidly create assertions (a full report on this event by Richard Goering is posted here ) . As it turns out, one of these case studies -- the presentation by...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Thu, Apr 28 2011
DVClub: Verification Users Discuss Assertion Challenges and Solutions
Assertion-based verification has many advantages, but is not particularly easy to use. At Silicon Valley DVClub April 26, two engineers discussed the benefits and challenges of assertions, and described their experience with two tools that help answer the question, "who's going to write all...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Apr 26 2011
User View: Why and How to Use Transaction-Based Acceleration
Transaction-based acceleration can speed up simulation hundreds of times, but you need to develop a good strategy to take full advantage of it, according to a paper authored by Cadence and Broadcom and presented at the recent DVCon conference . The paper detailed Broadcom's experience using transaction...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 23 2011
Broadcom Presentation Shows Value of Transaction-Based Acceleration
Wow - what a paper! At CDNLive! Silicon Valley 2010 , the joint paper from Broadcom and Cadence, titled Transaction-Based Acceleration: Strong Ammunition in any Verification Arsenal , showed evidence that simulators are running out of steam for system level simulations. At Broadcom, simulators certainly...
Posted to
System Design and Verification
(Weblog)
by
rmathur
on Tue, Nov 16 2010
User Interview: Easing Analog/RF IP Creation And Integration
Analog and RF IP creation isn't easy in this era of rising complexity and shrinking process nodes. Supporting the integration of IP into SoCs poses many difficulties as well. Jacob Rael, senior manager at Broadcom , is an analog/RF designer who knows these challenges well. In the short video interview...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jul 21 2010
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