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  • help with non-existent pin

    Hi All, We're trying to run a post extracted simulation and the simulator won't netlist. Error message reads: ERROR (OSSHNL-249): There is no corresponding terminal for 'zorchp' (on placed master 'ind_diff_1p95n_ef/layout') in.... A long time ago when I was doing the layout of...
    Posted to Custom IC Design (Forum) by linbo on Tue, Oct 9 2012
  • Re: How to perform Post-Layout simulations using UltraSim for Black-Box Cells?

    Hi Quek Thanks for your reply. I specified the dpf file as per your advice and the simulation has completed successfully and a graph is also plotted but results are not correct! Actually ultrasim is not able to find the 'INVXL' subcircuit. (which is Artisan's standard cell). Here is the message...
    Posted to Custom IC Design (Forum) by BraveHeart on Wed, Oct 26 2011
  • ADE L | post-layout simulation | input.scs error | missing model

    Hi, after successful RLC extraction I got a av_extracted view, which I set in ADE Setup->Environment... in the Switch View List in order to perform post-layout simulation. The netlist is created without any error. However, when I start to run a transient simulation I get te following error: <<...
    Posted to Custom IC Design (Forum) by pitter on Sat, Nov 7 2009
  • Re: Assura QRC extraction problem

    I am experiencing exactly the same problem. Apparently it has nothing to do with the PDK since I am having the same extraction problem for several design kits (AMS350, UMC 180nm and UMC130nm). The same problem does not appear when runing the extraction with DIVA, but I have some limitations for DIVA...
    Posted to Custom IC Design (Forum) by miguelUA on Tue, Apr 21 2009
  • my problem with assura RCX

    hi,guys These days I am doing a layout,I set up vdd and gnd as input pins and label in the layout.After I run a rcx to extract the RC parasitics,backannotate and find that, the pcapacitors are displayed without the presistor, it showed "r=NA". In the CIW, it prompts no DC path warning. But...
    Posted to Custom IC Design (Forum) by mighty on Mon, Nov 10 2008
  • C-only RCX extraction question

    Hi, I ran a post-layout C-only RCX extraction to generate an av_extracted cell and probed each of the nodes of my layout to get the capitances at each node. The weird thing is if I use ideal caps with the values of these capacitances and place them on an identical schematic and run simulations, the results...
    Posted to Custom IC Design (Forum) by Heartilly2000 on Thu, Sep 18 2008
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