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assertions,analog assertions,Functional Verification

  • Digital and Analog Verification – Round Peg in a Square Hole?

    Recently I wrote about a panel discussion that looked at ways of bridging the gap between analog and digital design. This blog post resulted in a lengthy discussion in a LinkedIn group that brought up the topic of verification. One commentator noted that analog and digital designers have very different...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Feb 9 2012
  • DVCon Wrap-Up and Blog Review

    The DVCon conference, held Feb. 28-March 3 in San Jose, Calif., was by all appearances a success this year. Major events were well attended and the program had a lot of interesting content. While the Universal Verification Methodology (UVM) was a major focus, this year's program made it clear that...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Mar 10 2011
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