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architect,embedded software

Equine Anatomy, Pax Romana and the Reach of Standards

At the recent Synopsys EDA Interoperability Forum, the opening session focused on a 10 year review of standards and interoperability between EDA tools. Three speakers -- Philippe Magarshack (Central R&D Group VP, STMicroelectronics), John Goodenough (Vice-President of Design Technology and Automation...

Posted to System Design and Verification (Weblog) by fschirrmeister on Wed, Dec 14 2011
Building Open Virtual Platforms - Bridging the Gap of Model Availability

Virtual prototypes promise to enable early software development, shorten system bring-up time, and provide a resulting increase in revenue. One of the key barriers that project teams face when considering use of virtual prototypes is the "missing model syndrome" -- essentially the lack of adequate...

Posted to System Design and Verification (Weblog) by Steve Brown on Wed, May 4 2011
Way Worse Than The Real Thing

This week Cadence and Virtutech announced a collaborative effort to bring together the Virtutech Simics virtual platform with the Cadence ISX software testing system. This is a very interesting combination of technologies, clearly demonstrating how virtual platforms make it possible to test software...

Posted to System Design and Verification (Weblog) by TeamESL on Mon, May 18 2009
SystemC TLM2 based Virtual Prototype Demo at DVCon

DVCon 2009 promises much news about System level design and verification. With Open SystemC Initiative (OSCI) events such as the SystemC Users Group , and a TLM2 Modeling and Interoperability Tutorial , there's much to learn and contribute at the event. Cadence will have a booth and one of the demos...

Posted to System Design and Verification (Weblog) by Steve Brown on Tue, Feb 17 2009
System-level design and verification - at the center!

This year, Cadence increases its focus on system-level design and verification events. During the latest CDNLive San-Jose that was held in September, the guest keynote - Dr. Jan Rabaey, Distinguished Professor of Electrical Engineering at the University of California, Berkeley, described the challenges...

Posted to System Design and Verification (Weblog) by Ran Avinun on Tue, Oct 7 2008

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architect,embedded software

Equine Anatomy, Pax Romana and the Reach of Standards

Building Open Virtual Platforms - Bridging the Gap of Model Availability

Way Worse Than The Real Thing

SystemC TLM2 based Virtual Prototype Demo at DVCon

System-level design and verification - at the center!