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apps

DAC 2012 Preview: Focus on Formal and ABV Events and Papers

In a few short weeks DAC 2012 will be upon us (June 3-7, 2012 in San Francisco, CA) , and Team Verify and our colleagues on the Incisive Verification team will be there in force with detailed briefings, panels, papers, posters, and of course live demos in the Cadence booth. Here are the formal and assertion...

Posted to Functional Verification (Weblog) by TeamVerify on Mon, May 14 2012
Video Tech Tip: Data Path Verification Using a Formal Scoreboard with Incisive Formal Verifier

This 6 minute video is a quick overview of our formal scoreboard app. Specifically, the video references the same AXI bridge example included with Incisive Formal Verifier (IFV) and Incisive Enterprise Verifier (IEV) so you can follow along on your workstation! If video does not open, click here . If...

Posted to Functional Verification (Weblog) by TeamVerify on Tue, May 8 2012
CDNLive Silicon Valley 2012: Much More than Moore

Last week I had the pleasure of meeting dozens of customers at CDNLive! Silicon Valley, and learning from the keynotes, in-depth technical papers, and synchronistic conversations throughout the event. Below are some highlights and themes that emerged. Left to right: Keynote speakers Lip-Bu Tan (Cadence...

Posted to Functional Verification (Weblog) by jvh3 on Tue, Mar 20 2012
CDNLive! – Lip-Bu Tan Keynote Cites Semiconductor Growth Drivers

CDNLive! Silicon Valley , the annual Cadence U.S. user conference, opened in San Jose, California March 13, 2012 on an optimistic yet cautionary note. Keynote speakers from Cadence, TSMC and ARM each predicted a new era of innovation in the electronics industry, but also noted daunting challenges that...

Posted to Industry Insights (Weblog) by rgoering on Tue, Mar 13 2012
DVCon 2012 Video: Product Engineer Chris Komar Reviews the Tutorial on Formal Apps

In this interview Product Engineer Chris Komar recaps the tutorial on formal apps given on Thursday March 1, 2012 at DVCon. Chris outlines how the "apps" approach can tackle verification challenges that are relatively easy for formal and formal+simulation to solve, and backs this up with some...

Posted to Functional Verification (Weblog) by TeamVerify on Thu, Mar 8 2012
DVCon Panel: Will Differentiation Through Software Kill Chip Design?

Will systems-on-chip (SoCs) become so expensive to design that people are going to buy chips off the shelf, and differentiate products through software alone? That's one question that was put before a panel of EDA industry experts at the DVCon conference Feb. 29, 2012. Short answer -- no, but we...

Posted to Industry Insights (Weblog) by rgoering on Thu, Mar 1 2012
DVCon 2012 Preview: Focus on Formal & ABV Events and Papers

In a few short weeks DVCon 2012 will be upon us ( Feb. 27 - March 1 in San Jose ), and Team Verify and our colleagues on the Incisive Verification team will be there in force supporting tutorials, panels, papers, and of course the afternoon expo with our partners. Focusing on the formal and assertion...

Posted to Functional Verification (Weblog) by TeamVerify on Tue, Feb 14 2012
2012 CES: Top 3 Trends Impacting EDA This Year

For years now consumer electronics have driven (nay, saved) the EDA industry. Hence, many events at last week's annual Consumer Electronics Show (CES) in Las Vegas can be extrapolated as leading indicators for the EDA business. While I couldn't personally attend CES this year, I had two trusted...

Posted to Functional Verification (Weblog) by jvh3 on Tue, Jan 17 2012
Cadence OrCAD Capture Marketplace -- The Cool Factors

Hey, did you hear about the new Cadence OrCAD Capture Marketplace? It has the first-of-its-kind PCB online store for “apps” and literally makes finding PCB centric stuff really easy to find. That’s cool! No more having to leave Capture to open a browser to search for a part or a symbol...

Posted to PCB Design (Weblog) by Team OrCAD on Tue, May 17 2011
Panelists: A Reality Check on Hardware/Software Co-Design and Co-Verification

Is hardware/software co-development ready for prime time? Yes, but much remains to be done, according to panelists at the May 12 EE Times System on Chip "Virtual Event." Panelists discussed hardware/software partitioning, benefits of co-design and co-verification, barriers to adoption, what's...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 16 2011

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apps

DAC 2012 Preview: Focus on Formal and ABV Events and Papers

Video Tech Tip: Data Path Verification Using a Formal Scoreboard with Incisive Formal Verifier

CDNLive Silicon Valley 2012: Much More than Moore

CDNLive! – Lip-Bu Tan Keynote Cites Semiconductor Growth Drivers

DVCon 2012 Video: Product Engineer Chris Komar Reviews the Tutorial on Formal Apps

DVCon Panel: Will Differentiation Through Software Kill Chip Design?

DVCon 2012 Preview: Focus on Formal & ABV Events and Papers

2012 CES: Top 3 Trends Impacting EDA This Year

Cadence OrCAD Capture Marketplace -- The Cool Factors

Panelists: A Reality Check on Hardware/Software Co-Design and Co-Verification