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analog,mixed-signal,low power

CDNLive! 2012 Proceedings – Over 150 User Presentations on Design and Verification

A fantastic resource is available for chip and system designers -- proceedings from five of the CDNLive! Conferences held in 2012. By my count this includes over 150 user-authored presentations given at CDNLive! Silicon Valley (March 12-13), CDNLive! EMEA (May 6-8), CDNLive! Taiwan (July 11), CDNLive...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 9 2013
Mixed-Signal Methodology Guide Sets New Directions for SoCs

Nearly all systems-on-chip (SoCs) these days are mixed-signal, with increasingly complex analog/mixed-signal (AMS) IP blocks. Meanwhile, analog blocks increasingly contain digital control logic. Yet analog and digital design are still done in relative isolation, using very different methodologies and...

Posted to Industry Insights (Weblog) by rgoering on Wed, May 30 2012
12 Hot EDA Topics – 78 DAC Demo Sessions

Whatever your role in the chip or system design process, there is probably a Cadence demo geared to your interests at the Design Automation Conference ( DAC 2012 ) June 3-7 in San Francisco. Cadence has three demo suites at its booth (#1930) and is running one-hour demos from 10:00 am to 5:00 pm Monday...

Posted to Industry Insights (Weblog) by rgoering on Thu, May 24 2012
Managing Inherited Connections with CPF in Virtuoso

Let's assume you are managing a schematic-driven top level design in Virtuoso and you want to import a digital block Verilog netlist into Virtuoso. This is a very common use model in mixed-signal implementation. While the Layout Database is saved in Open Access (OA), the optimized Verilog netlist...

Posted to Mixed-Signal Design (Weblog) by AndreasLenz on Wed, May 23 2012
Free DAC Lunches: Custom/Analog Variability, ARM Low Power Processors in Mixed-Signal Designs

There is such a thing as a free lunch - if you're at the 49th Design Automation Conference (DAC) in San Francisco June 3-7. Cadence is sponsoring two lunches at which you can learn about two important technology topics - custom/analog variability, and the use of ARM processors in low-power, mixed...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 14 2012
Learn How to Do Mixed-Signal Design at CDNLive! Silicon Valley

With the theme of Connect, Share and Inspire, this year's CDNLive! Silicon Valley March 13-14, 2012 will be an exciting forum for Cadence customers to share their most recent chip design successes and learn from each other. Among close to 100 presentations during the packed two day agenda, one area...

Posted to Mixed-Signal Design (Weblog) by QiWang on Wed, Mar 7 2012
Webinar Report: Power-Aware Mixed-Signal Verification

Most of the discussion about low-power design techniques has focused on digital circuits. However, nearly all systems-on-chip (SoCs) are mixed-signal, and the way in which analog and digital circuitry interact has a huge impact on overall power consumption. Thus, low power (or "power aware"...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 25 2012
Webinar Report: Solving Mixed-Signal Power Grid Challenges

Complex analog/mixed-signal ICs pose many power grid design and analysis challenges. Unanticipated IR drop and electromigration problems are commonplace, and they significantly impact circuit behavior. But as a recently archived webinar shows, there are a number of ways to minimize these problems, even...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 11 2012
All Things Analog – Video Interviews with Experts

John Pierce, product marketing director at Cadence, recently sat down with several analog/mixed-signal design and verification experts for "All Things Analog" video interviews. These short (8-11 minute) video clips offer some good insights into analog verification and simulation, PLL design...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 4 2012
GTC Panel: Getting Best Use From Older IC Process Nodes

Time for a mainstream revolution? That was the title of a lively panel discussion at the Global Technology Conference ( GTC ) Aug. 30. Panelists noted that there's still a lot of activity at 65nm and above. They discussed why this is true, whether mature nodes can be retrofitted with new capabilities...

Posted to Industry Insights (Weblog) by rgoering on Mon, Sep 5 2011

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analog,mixed-signal,low power