	Login with a Cadence account.
Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register \| Membership benefits

Get email delivery of the Cadence blog (individual posts).

Popular Tags

Browse All Tags

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

analog

CADENCE capacitor corners max min typ meaning

Hi all, Please anyone can tell me what is the meaning of max, min, and typ for capacitors corners. I understand that the parameters ss or ff corresponds to the mobility ( slow slow, fast fast) of the electrons in MOS devices. But i don´t understand what are the changes in the model of the capacitors...

Posted to Mixed-Signal Design (Forum) by Ricardo Alves on Mon, Jun 17 2013
Virtuoso Verilog Environment for NC-Verilog integration

Hi all, Through Virtuoso Verilog Environment for NC-Verilog Integration ，I initialize a analog design ,then setup netlist explicitly option to ture. I hope to generate that the netlister used the pin name method as following . The result is out of my expectation. some part of netlist remain the pin order...

Posted to Mixed-Signal Design (Forum) by Provence on Wed, Jun 5 2013
A CPF User Perspective on IEEE 1801 (UPF) “Methodology Convergence”

By leveraging Common Power Format (CPF) constructs and removing some older Unified Power Format (UPF) commands, the emerging IEEE 1801-2013 standard (UPF 2.1) will help enable "methodology convergence" with CPF. Kamran Haqqani, principal engineer at Maxim Integrated, will be happy to see this...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 13 2013
GCC_3.3.1 not found (required by /usr/lib/libX11.so.6

Hi, When I do the Verilog XL integratio in virtuoso and try to see the "Viewwaveform" , I do not get any window. Simulation of the verilog file gose fine.

Posted to Mixed-Signal Design (Forum) by KR1089 on Sun, Apr 14 2013
Step a bus signal from ADE-XL design variable

Hi, Is there a way for me to use design variables in ADE-XL to step through all possible values in a bus, say a_signal<3:0>, and run a DC simulation for each step? Regards, Daniel

Posted to Mixed-Signal Design (Forum) by daasboe on Wed, Apr 10 2013
Unleashing Mixed-Signal Tech on Tours (ToTs) in North America

At CDNLive-Silicon Valley this year, we had an excellent mixed-signal track for two days. Cadence customers including IBM, Texas Instruments, Maxim and Freescale shared their mixed-signal methodologies and tricks with the Cadence design community. The key challenges that our mixed-signal customers face...

Posted to Mixed-Signal Design (Weblog) by Sathish Bala on Fri, Mar 29 2013
Engineer Video: Best Practices for Mixed-Signal SoC (MS-SoC) Verification

Why is there a need for "best practices" in mixed-signal SoC verification, and what are some of those practices? A presentation at the recent DVCon 2013 conference addressed these questions by showing how Maxim Integrated is bringing digital techniques into mixed-signal verification. Here's...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 27 2013
"Smart Devices" and How They Affect Your Mixed-Signal SOC Verification

We are seeing a huge trend -- the mobile revolution is changing the way we go about our everyday lives. Gone are the days where the term 'Internet' was associated with a PC or Mac. The smartphone revolution has changed how the data is consumed and used by consumers and businesses. For example...

Posted to Mixed-Signal Design (Weblog) by Sathish Bala on Mon, Feb 25 2013
New Book: Analog Design and Simulation Using OrCAD Capture and PSpice

Thousands of engineers worldwide use OrCAD Capture for PCB schematic entry and PSpice for circuit simulation. These popular products, both provided by Cadence, deserve a good "how to" book -- and now they have one. It's titled " Analog Design and Simulation Using OrCAD Capture and...

Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 20 2013
Introduction to Cadence Virtuoso Advanced Node Design Environment

What can designers do about advanced node technology? This is an introduction to the Cadence Virtuoso Advanced Node design environment, announced Jan. 28, 2013, as a custom/analog design development environment for leading edge-advanced node technology. Problems of Advanced Node Design When designing...

Posted to Custom IC Design (Weblog) by Hiro Ishikawa on Mon, Jan 28 2013

Page 1 of 13 (129 items) 1 2 3 4 5 Next > ... Last »

Popular Tags

Email

Share

Subscribe

Contact Us

analog

CADENCE capacitor corners max min typ meaning

Virtuoso Verilog Environment for NC-Verilog integration

A CPF User Perspective on IEEE 1801 (UPF) “Methodology Convergence”

GCC_3.3.1 not found (required by /usr/lib/libX11.so.6

Step a bus signal from ADE-XL design variable

Unleashing Mixed-Signal Tech on Tours (ToTs) in North America

Engineer Video: Best Practices for Mixed-Signal SoC (MS-SoC) Verification

"Smart Devices" and How They Affect Your Mixed-Signal SOC Verification

New Book: Analog Design and Simulation Using OrCAD Capture and PSpice

Introduction to Cadence Virtuoso Advanced Node Design Environment