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allegro

  • Same net via to via spacing drc suppressed

    In SPB 16.3 hotfix 20 (maybe implemented in 18) Allegro Constraint manager will no longer report a same net via to via spacing drc if those vias are covered (direct connect) by a shape. Cadence says that once the via is covered with a shape the pad ceases to exist and it simply becomes a hole to hole...
    Posted to PCB Design (Forum) by Idaho Tom on Mon, Dec 6 2010
  • line to shape spacing error

    Hi All I have attached a doc .Please go through that doc for clarifying my doubt. I poured a dynamic copper shape for ground over the ground pin which is already connected by tracks. It shows line to shape DRC. Whether i have to add any property to that particular net alone or i have to do it in different...
    Posted to PCB Design (Forum) by Anonymous on Thu, Dec 2 2010
  • What's Good About Mechanical Parts in ADW? Check Out the ADW16.3 Release and See!

    Mechanical part support! It's here in the Allegro Design Workbench (ADW16.3) release! There are new data model types in ADW16.3 that provide a solution for the support of mechanical models in the library and design flow. The mechanical model types supported in this release include three basic model...
    Posted to PCB Design (Weblog) by Jerry GenPart on Wed, Dec 1 2010
  • ADDING VIA TO ALLEGRO 15.2 VER LAYOUT

    Hi All How to bring in newly added via pads in allegro 15.2 version? I created 12/24 & 24/40 via padstacks and added it to library and updted my pad path& psmpath After this i don no how to proceed to bring via in Can anyone reply me soon. Regards ARFAJ SANDS
    Posted to PCB Design (Forum) by Anonymous on Wed, Dec 1 2010
  • converting .max file to .brd file

    Hi All Can anyone say me where to download conversion file (from .max to .brd). I tried in cadence software downloads but i cant fint the software.Is there any easy way to solve this conversion.Waiting for reply.Thanks in advance ARFAJ(SANDS)
    Posted to PCB Design (Forum) by Anonymous on Thu, Nov 25 2010
  • converting library footprints from protel to allegro

    Hi All, I have some basic doubt in converting library footprints from protel to allegro. Is it possible to convert ? Moreover am using allegro 15.2ver .In this there is no option to import protel board files. It has only import-->pads & pcad. Please help me with the procedure to do this if its...
    Posted to PCB Design (Forum) by Anonymous on Thu, Nov 25 2010
  • What's Good About Part Developer and Fonts? You Can Change Them in SPB16.3!

    PCB Librarian Expert (sometimes known as Part Developer or PDV ) is the librarian tool used for generating all the parts that are used in Allegro Design Entry HDL (DEHDL) and Allegro System Architect (ASA) based designs. These parts contain symbols which are placed on the schematic canvas and connected...
    Posted to PCB Design (Weblog) by Jerry GenPart on Tue, Nov 23 2010
  • A Shorter, Predictable Design Cycle for Complex PCBs - Dynamic Phase Control

    This is second in a series of blog posts about making your design cycles shorter and more predictable for increasingly complex PCB designs. In my last post I talked about using ECSets and Topology Apply capabilities for high-speed standards based interfaces such as DDRx and PCI Express. Continuing on...
    Posted to PCB Design (Weblog) by hemant on Thu, Nov 18 2010
  • Create a void from a shape in Allegro

    Hi all, I am trying to create a ring of exposed copper at the edge of a board by creating a shape on the solder mask top, however I can't seem to make an actual ring rather than a big filled plane. I can use z-copy to get the outer edge from my route keepin, but I can't figure out how to use...
    Posted to PCB Design (Forum) by spbae on Tue, Nov 16 2010
  • What's Good About Allegro GRE Planning? You’ll Need the SPB16.3 Release to See!

    This new SPB16.3 Global Route Environment (GRE) Plan Status and Router Status functionality will assist you in finding errors and is designed to make it easier to work with the router and obtain feedback from the router. It employs a Constraint Manager type spreadsheet interface with cells that are active...
    Posted to PCB Design (Weblog) by Jerry GenPart on Wed, Nov 10 2010
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