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advanced verification,uvm

  • What Does it Take to Migrate from e to UVMe?

    So you are developing your verification environment in e , and like everyone else, you've been hearing a lot of buzz surrounding UVM (Universal Verification Methodology). Maybe you would also like to give it a try. The first question that pops in your mind is, "What would it take to migrate...
    Posted to Functional Verification (Weblog) by teamspecman on Wed, Sep 5 2012
  • UVM Testflow Phase Debugging- Identifying Blocking Activities

    UVM Testflow debugging capabilities have been recently enhanced through the addition of more information to the output of the show domain command. In this post, we demonstrate how this information can be used to answer such questions as 1. What domains are in the environment? What units do they contain...
    Posted to Functional Verification (Weblog) by teamspecman on Mon, Jul 16 2012
  • What’s Next in Low Power?

    Low power has become a major consideration in chip design in almost all applications. One major achievement of the industry over the past a few years is the alignment on the low power design methodology, which was considered as the biggest hurdle to automate advanced low power design techniques. No matter...
    Posted to Low Power (Weblog) by QiWang on Tue, Jan 24 2012
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