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advanced node
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wreals
GLOBALFOUNDRIES at CDNLive: Why 10nm Requires Design Technology Co-Optimization
It's not too early to start thinking about the 10nm process node and beyond - but such advanced process nodes will require a significant change in the semiconductor design ecosystem, according to Jongwook Kye, fellow for lithography modeling and architecture at GLOBALFOUNDRIES. At the recent CDNLive...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Apr 29 2013
CDNLive Silicon Valley 2013 Proceedings Available for Download!
CDNLive Silicon Valley, held March 12-13, 2013, featured nearly 100 technical sessions from customers, partners, and Cadence R&D experts. Presentations from most of those sessions are now available on line . Here's your chance to review presentations you heard, catch up on sessions you missed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Apr 4 2013
Virtuosity: 10 Things I Learned in February By Browsing Cadence Online Support
February was a big month for RAKs (Rapid Adoption Kits)! If you haven't checked out the listings under Resources->Rapid Adoption Kits yet, you're missing out. You'll find databases with detailed instructions, documentation and videos on many tools, features and flows. They've become...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Mon, Mar 18 2013
Introduction to Cadence Virtuoso Advanced Node Design Environment
What can designers do about advanced node technology? This is an introduction to the Cadence Virtuoso Advanced Node design environment, announced Jan. 28, 2013, as a custom/analog design development environment for leading edge-advanced node technology. Problems of Advanced Node Design When designing...
Posted to
Custom IC Design
(Weblog)
by
Hiro Ishikawa
on Mon, Jan 28 2013
Top Ten Cadence Community Blog Posts of 2012
In 2012, Cadence Community bloggers turned out over 400 posts in categories including Industry Insights, Functional Verification, PCB, IC Packaging, Custom IC, System Design and Verification, RF, Low Power, Mixed Signal, Logic Design, and Digital Implementation. Below is a listing of the ten most read...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jan 1 2013
Archived Webinar: Variation-Aware Analysis for Advanced Node Design
Why is variation such a big problem at 45nm and below, and what can custom/analog designers do to analyze and mitigate it? A new series of Cadence webinars on "variation-aware design" helps answer these questions. This blog post reviews the first webinar in the series, which was offered Nov...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Nov 11 2012
Video: Cadence VP Tom Beckley Discusses Advanced Node Custom/Analog Challenges
Any discussion about advanced node (below 28nm) that focuses only on digital design is missing an important part of the story. Custom/analog design must be considered too, and that's the subject of a video interview with Tom Beckley, senior vice president of R&D for Custom IC and Simulation at...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 5 2012
20 Questions on 20nm – And a New Resource for Advanced Node Design
If you're currently doing or contemplating IC design at 28nm and below, you no doubt have some questions. One place to get a lot of them answered is an Advanced Node microsite newly launched by Cadence for both digital and custom/analog designers. And one interesting (and new) document you'll...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jul 26 2012
What’s Hot for Mixed-Signal At DAC?
Analog/mixed-signal design is a hot topic at the Design Automation Conference! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), you can keep up with the latest developments in mixed-signal design methodology, including design, implementation and verification. You will find it is...
Posted to
Mixed-Signal Design
(Weblog)
by
QiWang
on Thu, May 31 2012
“In Design” DFM Signoff – the Inside Story
As noted in a recent customer announcement with Fujitsu, Cadence offers "in design" design for manufacturability (DFM) signoff for digital, mixed-signal and custom IC design. The basic idea is simple - engineers run signoff DFM checks during the physical design process, instead of waiting until...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Oct 5 2011
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