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abstract

  • abstractgen error (abs-1427 and ABS-520)

    Hi , I'm having this error int the Pin creation part. Can anyone tell me how to overcome this?.. 11/28/13 18:52:23: ERROR (ABS-1427): Could not create pin from shape because 11/28/13 18:52:23: ERROR (ABS-1427): Could not create pin from shape because 11/28/13 18:52:23: ERROR (ABS-1427): Could not...
    Posted to Custom IC Design (Forum) by jorenrefuerzo on Thu, Nov 28 2013
  • Problem while loading abstract view in Encounter 11.13

    Hai, I converted the virtuoso layout design in abstract view and loaded it in encounter. It shows error as below. **ERROR: (ENCOAX-1295): The openAccess design referred by the lib/cell/view - 'dfetx/dfetx/abstract' is abstract view type and cannot be opened in Encounter. ERROR: **ERROR: (ENCVL...
    Posted to Digital Implementation (Forum) by selvam27 on Tue, Nov 5 2013
  • Abstract Generation Crashes during Step pins in a given cell

    whenever i try to run this given cell , the abstract generation run experience system crash. heres the part of log file. WARNING (ABS-523): Cell misc_dtr: The pin iptat20u has shape on an invalid user layer numbered 25 in the technology file. The pin will be deleted from the layout. INFO (DB-170018)...
    Posted to Custom IC Design (Forum) by jorenrefuerzo on Wed, Sep 4 2013
  • help with Abstract generator

    Dear friends First of all I take this oppertunity to say hi , I hope to have a great, honorable and informative virtual kinship with all of you. The problem I am facing is with the Abstract generator, I have a few verilog modules that are nested and I have created their GDS through encounter. I imported...
    Posted to Custom IC Design (Forum) by sardar1 on Wed, Jun 19 2013
  • Generating LEF from layout view

    Hi all! I have been trying to export LEF from standard cells layout in order to use that LEF file in Encounter for automatic PnR. From virtuoso I select File -> Export -> LEF and fill the form appropriately but the lefout.log is giving a warning on metal 4 as shown below: Warning (OALEFDEF-50144...
    Posted to Custom IC Design (Forum) by BraveHeart on Tue, Jun 12 2012
  • Abstract generator ver 5.6

    Dear Sir, I am using Abstract genertor 5.6. The exact version detail is @(#)$CDS: ui version 6.1.3. 02/05/2009 20:51 (cic612lnx) $ But I am getting these warning/error *WARNING* dbDeleteShape: A memory allocation for 2147483648 bytes failed. The process heap is 1047MB, and OpenAccess is using 1039MB...
    Posted to Custom IC Design (Forum) by Satendra on Wed, Feb 2 2011
  • Re: connections to abstract not verified by Assura LVS - what's wrong?

    I spoke with our foundry's support team, and I experimented some more. I finally got it working. Here's what I learned: The black box's schematic cannot be empty. It must contain at least one device (cds_thru, presistor, some transistor, etc.). If it does not, Assura LVS will prune it from...
    Posted to Custom IC Design (Forum) by TrevorB on Wed, Jan 13 2010
  • Re: connections to abstract not verified by Assura LVS - what's wrong?

    Hi Quek, Thanks for your reply. To answer your questions: 1) I cannot find the IP block's cellName even mentioned in the design.erc file. 2) The layout and schematic are both df2 - no GDS2. 3) I found the following rules in my extract.rul file: ;; ;; >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>...
    Posted to Custom IC Design (Forum) by TrevorB on Sat, Jan 9 2010
  • connections to abstract not verified by Assura LVS - what's wrong?

    Hi, We are using an IP block from our foundry in our chip. The IP block is located below the top level of the hierarchy. And, the IP block is presented as an empty layout block, containing only pins and boundary shapes. Currently, as we run Assura LVS with the default options, our outside connections...
    Posted to Custom IC Design (Forum) by TrevorB on Thu, Jan 7 2010
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