Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
More Products
OrCAD Products
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
IP Alliances
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Quicklinks
All Blogs
All Forums
Community Search
CDN
Live!
User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> Xuropa
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
All Blog Categories
Popular Tags
Allegro
ARM
Custom IC Design
DAC
Digital Implementation
e
EDA360
encounter
ESL
Functional Verification
Incisive
industry insights
Logic Design
Low power
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
SystemVerilog
TLM
UVM
verification
Virtuoso
Browse All Tags
Share
Email
Social Web
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
Xuropa
acceleration
Amazon
Cadence
Cadence VIP portfolio
CDNLive
CDNLive San Jose 2008
chip estimate
cloud
cloud computing
Colgan
coverage metrics
DAC
DAC party
Denali
DVcon
e
EDA Consortium
EDP
ESC
events
Formal Analysis
formal verification
Functional Verification
funtional verification
Griffith
Harry The ASIC Guy
Hosted Design Services
Hosted Design Solutions
IaaS
IES-XL
Incisive
Industry Insights
IntelliGen
IP
IP Evaluation
Kuehlmann
memory models
MIPI
OVM
PaaS
Palladium
PCI Express
protocols
SaaS
Simulation
Specman
testbench interface
USB
UVM
verification
Verification IP
verification plan
VIP
VIP Catalog
vPlan
Best Practices for Selecting and Using Verification IP (VIP)
In the past few years, commercial verification IP (VIP) has been selected for use in an ever greater percentage of verification environments. While VIP has the capability to save considerable time and engineering resources, there are several decisions you need to make in order to optimize the value received...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Feb 13 2012
Cadence Denali Acquisition Results in Broad Verification IP (VIP) Offering
High-tech mergers succeed when two companies blend their technologies and expertise to come up with a "best of both" solution. That's the idea behind today's (Feb. 28, 2011) Cadence Verification IP (VIP) catalog announcement , which combines VIP and technology that originated at both...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Feb 28 2011
DAC Panel: A Reality Check On Cloud Computing For EDA
Does IC design have a future "in the clouds?" Yes, according to panelists at last week's Design Automation Conference - but selectively, over a period of time. As attractive as cloud computing is, there are still technology challenges and tradeoffs, and the EDA licensing model for cloud...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jun 23 2010
DAC Panel Looks To “Clouds” For EDA
Does IC design have a future in cloud computing? What are the real and perceived obstacles, and how can they be overcome? A Design Automation Conference panel will discuss these questions Wednesday, June 16, from 2:00 to 4:00 pm in Anaheim, Calif. Andreas Kuehlmann, director of Cadence Research Labs...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 26 2010
Presentation: Rethinking Software-as-a-Service For EDA
One of the more startling statements at the recent Electronic Design Processes (EDP) workshop came in a presentation from James Colgan, CEO of Xuropa . At one point he appeared to be saying that software-as-a-service ( SaaS ) is not the right model for EDA, at least not for quite some time. But Xuropa...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Apr 21 2010
IntelliGen Lab Now Live on Xuropa - See What You Are Missing!
Team Specman guesstimates that a majority of users have migrated to "IntelliGen" -- the all new, Aspect-Oriented generation engine inside of Specman and IES-XL, and/or they are in the process of adopting IntelliGen now. However, in case your CAD configuration is just becoming unfrozen after...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Nov 10 2009
Cadence’s Xuropa Experience – A New Approach To IP Evaluation
Evaluating EDA software or silicon IP is an arduous process that often requires negotiated license agreements, software downloads, installation, and the physical presence of a jet-lagged AE who just flew across the country. What if you could run an evaluation instantly on line, and skip all that? That’s...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 30 2009
Survey Results For "Booth-Centric" vs. "Paper Centric" Shows
In my last post I shared how my annual tour of the tour of the ESC show floor inspired me to ask the community their preferences on trade show formats. Since I'm not certain how persistent these free survey sites are, allow me to replicate a snapshot of the survey results from the official results...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Tue, Apr 14 2009
DVCon '09 SaaS Panel Thoughts, Part 3
In my previous posts on the DVCon 2009 panel on Software As A Service, or "SaaS" as it applies to EDA, recall that the main issues that came up were: Security ( the focus of Part 2 of this series ) EDA applications that can clearly benefit from SaaS Bandwidth needs Configuration control Dealing...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Mon, Mar 30 2009
Experiment With Cadence's MIPI VIP Live in The Xuropa Online Lab
At risk of being lost in all the excitement of DVCon 2009 last week , my colleagues on the VIP Team announced a truly unique experiment, where the whole MIPI Verification IP product is available to try out now in the Xuropa Online Lab . The important thing to note is that this is not some cheesy Flash...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Tue, Mar 3 2009
Page 1 of 1 (10 items)