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Virtuoso,simulation

  • ICCAD 2013: The New Electrically Aware Design Paradigm

    SAN JOSE, Calf.--Pop quiz: What percentage of verification time do design teams spend on re-iterating their layout design after checking electrical parameters? If you said 30-40 percent, move to the head of the class. And given the ceaseless increase in design complexity, you'd expect that percentage...
    Posted to The Fuller View (Weblog) by Brian Fuller on Tue, Nov 26 2013
  • IBIS model simulation

    I am designing a Data acquisition system with a Texas instruments ADC, Inamps and a ST micro electronics micro controller. I am getting spice models for my inamps, differential amplifiers etc. so that I could do SPICE simulation. I wish to see the output of my ADC if I am providing an input signal with...
    Posted to PCB Design (Forum) by niranjan madha on Wed, Apr 17 2013
  • Mixed Signal Technology Summit Proceedings Now Available

    In September 2012, Cadence held its second Mixed-Signal Summit in San Jose, California. 150 users attended the Summit. The full day program was packed by user presentations. Strong participation and attendance was yet another confirmation of increased design activities in the mixed-signal area. Attendees...
    Posted to Mixed-Signal Design (Weblog) by nizic on Thu, Dec 13 2012
  • Archived Webinar: Variation-Aware Analysis for Advanced Node Design

    Why is variation such a big problem at 45nm and below, and what can custom/analog designers do to analyze and mitigate it? A new series of Cadence webinars on "variation-aware design" helps answer these questions. This blog post reviews the first webinar in the series, which was offered Nov...
    Posted to Industry Insights (Weblog) by rgoering on Sun, Nov 11 2012
  • Learn How to Do Mixed-Signal Design at CDNLive! Silicon Valley

    With the theme of Connect, Share and Inspire, this year's CDNLive! Silicon Valley March 13-14, 2012 will be an exciting forum for Cadence customers to share their most recent chip design successes and learn from each other. Among close to 100 presentations during the packed two day agenda, one area...
    Posted to Mixed-Signal Design (Weblog) by QiWang on Wed, Mar 7 2012
  • Digital and Analog Verification – Round Peg in a Square Hole?

    Recently I wrote about a panel discussion that looked at ways of bridging the gap between analog and digital design. This blog post resulted in a lengthy discussion in a LinkedIn group that brought up the topic of verification. One commentator noted that analog and digital designers have very different...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Feb 9 2012
  • Webinar Report: Solving Mixed-Signal Power Grid Challenges

    Complex analog/mixed-signal ICs pose many power grid design and analysis challenges. Unanticipated IR drop and electromigration problems are commonplace, and they significantly impact circuit behavior. But as a recently archived webinar shows, there are a number of ways to minimize these problems, even...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 11 2012
  • Measuring Fmax for MOS Transistors

    The following question has come up in comments: "How do I measure F max for an MOS transistor?" The measurement methodology -- testbench, analysis, calculator setup, stimulus, etc.-- does not change whether you are measuring bipolar transistors or MOS transistors. On the other hand, the results...
    Posted to RF Design (Weblog) by Art3 on Thu, Aug 11 2011
  • Internal error with topology.c

    Hi, When I try to run a Spectre dc and trans simulation with my 8-bit-adder circuit, have an internal error stopping the simulation. I get the following messages in the spectre log window: 1) the usual "unable to compile ahdlcmi module library" message (which has not stopped my simulations...
    Posted to Custom IC Design (Forum) by CPete on Thu, Jun 2 2011
  • Calculation of Sub Threshold and Gate Leakage Power

    Dear Sir, I am working on 6t SRAM cell and want to calculate Sub Threshold and Gate Leakage power of that. So please help me and tell me the steps to calculate the sub threshold and gate leakage power.
    Posted to Custom IC Design (Forum) by Shyam Akashe on Mon, May 30 2011
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