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Virtuoso,icfb

  • How to not netlist a certain symbol

    Good day! I want to make library that when added to schematic, the instances are not netlisted during spectre simulation. The symbols does not have models and are designed for CDF parameter extraction only. I have a reference LIBRARY with this property but I can not find out how it was implemented. I...
    Posted to Custom IC SKILL (Forum) by alainmelan on Thu, Jul 3 2014
  • IBIS model simulation

    I am designing a Data acquisition system with a Texas instruments ADC, Inamps and a ST micro electronics micro controller. I am getting spice models for my inamps, differential amplifiers etc. so that I could do SPICE simulation. I wish to see the output of my ADC if I am providing an input signal with...
    Posted to PCB Design (Forum) by niranjan madha on Wed, Apr 17 2013
  • Problems Importing OA Design from Virtuoso into Encounter

    Hello, While trying to perform place and route using Encounter I'm "encountering" errors importing my design from Virtuoso. When I try to import the design, I get the following: Reading tech data from OA Library 'NCL' ... FE units: 0.001 microns/dbu, OA units: 0.001 microns/dbu...
    Posted to Digital Implementation (Forum) by TruLogic on Mon, Jan 10 2011
  • Using Spice Models/Netlists with icfb

    Hi all, I'm pretty new to the Cadence Environment and now I've got the task to make some simulations including some commercial PSpice models within the Cadence Environment (icfb, Virtuoso etc.). I found some information on the internet saying that this task could be done using "CDL in.....
    Posted to Custom IC Design (Forum) by mixedsignal on Tue, Dec 7 2010
  • CIW > File > Import > Verilog... fails to create schematics (portOrder property?)

    Hello I try importing the final verilog (.v) file generated by SoC encounter so I can do LVS for a mixed signal design, but ihdl.exe doesn't generate schematics. The beginning of the log file says (scgp is the digital library name in icfb): @(#)$CDS: ihdl.exe version 5.1.0 12/16/2007 23:32 (cicln04...
    Posted to Custom IC Design (Forum) by skylerweaver on Fri, Feb 12 2010
  • mapping file

    Help me how to use the mapping file to change the cells from one library to other library. In CIW -> ****_tools->Rereference standard cells is there any extension for the map file. It will be helpful with explanation how it will work and how to use. Regards Sathisha
    Posted to Custom IC Design (Forum) by sathisha on Tue, Jan 5 2010
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