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  • how to set the tech purpose of 0 in an ASCII technolog file

    I know the purpose of 0 is reserved by the system. But if I would like to use the purpose of 0, what's the name should I use? I can find other reserved purposes, such as 250 for 'boundary", 237 for 'label'. It seems 0 for 'unknown', however, if I use the 'unknown'...
    Posted to Custom IC Design (Forum) by phenixgj on Mon, Aug 2 2010
  • Things You Didn't Know About Virtuoso: ADE XL

    I know, it's been a long time since my last post. You see, we've finally arrived at a topic near and dear to my heart -- ADE XL. The reason for my hesitation in approaching this topic is not that it's difficult, but rather that there's so much to talk about that it's hard to know...
    Posted to Custom IC Design (Weblog) by stacyw on Tue, Jul 27 2010
  • Multiple Model Files

    Hi, I am working on a circuit where I need multiple model files. The first one I am using is gpdk045, I tried modifying this file to use with transistors from the analog library. The problem I have is that my simulations are wrong whenever I use a transistor with the second model file it just produces...
    Posted to Custom IC Design (Forum) by Karo on Wed, Jul 21 2010
  • ARM And Cadence Get To The “Core” Of Mixed-Signal Design

    An increasing number of analog and mixed-signal designs in automotive, power management, wireless, medical, and industrial applications require digital control. But designing a state machine, and integrating the increasing amount of logic gates that implements it, has been challenging for analog designers...
    Posted to Custom IC Design (Weblog) by nizic on Tue, Jun 8 2010
  • How to create templates for vdd/vss nets in Virtuoso

    I am working on the layout of a full custom digital design in Virtuoso. I have now fixed my pitch for the vdd and vss nets. Can anyone tell me as to how i can create templates of some sort of a ruler/guide for these nets which can help me to see where my vdd vss nets/tracks would lie in the layout .It...
    Posted to Custom IC Design (Forum) by akbhide on Mon, May 17 2010
  • Re: VerilogA Problem in MMSIM-7.1

    Hi !! I'm having a problem when trying to simulate a verilogA block. Gcc seems to be correctly installed and detected by MMSIM. We're using MMSIM 7.11 and IC5.1.41 (Cadence 2009-2010 IC package - icfb 5.1.0 subversion: within Linux Fedora 11 and with TSMC 0.18um Design Kit...
    Posted to Custom IC Design (Forum) by Winglet on Fri, May 14 2010
  • the sample library in dfII

    hi,there i have added the rfLib library which located in $CDS/tools/dfII/samples/artist directory to the ic5141 usr6 through library manager. But when i add the balun_com instance to the schematic,and start the simulation in the ADE,it gives the error message as below: ERROR: Netlister: unable to descend...
    Posted to Custom IC Design (Forum) by minci on Sat, Apr 10 2010
  • Filler Cells and Substrate Contacts in Virtuoso GXL

    Hi, I am using the student version of cadence tools at my Univ to auto place and route a custom design, using standard-cells. I am using the Custom IC tools suggested, i.e Schematic XL and Virtuoso GXL. I design the schematic of the architecture, first, then using the connectivity driven option, i generate...
    Posted to Custom IC Design (Forum) by nbtarun on Wed, Apr 7 2010
  • Things You Didn't Know About Virtuoso: It's Video Time!

    Just a quick post to let you know that there have recently been a whole truckload of videos added to the Cadence Online Support Video Library. (Some shameless self-promotion here--I created many of them...). Simply go to http://support.cadence.com (registration required) and choose Resources->Video...
    Posted to Custom IC Design (Weblog) by stacyw on Thu, Apr 1 2010
  • Cadence 6.1 problem

    Dear all, I know this might seem weird but it does happen to me.. I'm using cadence virtuso 6.1 for analog simulation. Sometimes I need the simulation to keep runing for the whole night, however, as soon as I leave it for some times, it just stops !!!, if return to my machine and start doing any...
    Posted to Custom IC Design (Forum) by Ayman Amin on Mon, Mar 29 2010
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