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Virtuoso

Step a bus signal from ADE-XL design variable

Hi, Is there a way for me to use design variables in ADE-XL to step through all possible values in a bus, say a_signal<3:0>, and run a DC simulation for each step? Regards, Daniel

Posted to Mixed-Signal Design (Forum) by daasboe on Wed, Apr 10 2013
Unleashing Mixed-Signal Tech on Tours (ToTs) in North America

At CDNLive-Silicon Valley this year, we had an excellent mixed-signal track for two days. Cadence customers including IBM, Texas Instruments, Maxim and Freescale shared their mixed-signal methodologies and tricks with the Cadence design community. The key challenges that our mixed-signal customers face...

Posted to Mixed-Signal Design (Weblog) by Sathish Bala on Fri, Mar 29 2013
Multi-VDD/Power-Gated Design VerilogIn

Hi, Is there a way for the multiple-vdd and/or virtual vdd nets to be properly generated during verilogIn? The import process relies on using the schematic and symbol definitions from the artisan_cell library that is provided to us and any cells that we have power gated or supplied a lower vdd to in...

Posted to Cadence Academic Network (Forum) by Northfork on Tue, Mar 26 2013
Re: Problem in Cadence Virtuoso AC analysis

Hi Andrew, I had a little doubt on what parameters are explicitly needed for ac analysis. This is because I am using verilog -A based models and hence want to be sure if I am doing the right thing. As far as I know, AC analysis first computes the DC operating point: so I must define current at each operating...

Posted to Custom IC Design (Forum) by OneNewBoy on Mon, Mar 25 2013
Power Difference between Analog Simulation and RTL complier estimation

Hallo, I am creating a standard cell library. I did analog simulation for cell design and estimated power values for the cells , lets say, NOT, NOR and NAND and I have their power values for static, dynamic, etc. Now based on that I created library file, and used that in RTL omplier for single cell designs...

Posted to Logic Design (Forum) by GreenGraphene on Mon, Mar 25 2013
Re: Problem in Cadence Virtuoso AC analysis

Hi Andrew, Thanks a lot for help. Please find below the contents of the netlist: // Generated for: spectre // Generated on: Mar 22 14:37:53 2013 // Design library name: Basic_Blocks // Design cell name: DiffAmp_MOS // Design view name: schematic simulator lang=spectre global 0 vdd! parameters C=2p Ibias...

Posted to Custom IC Design (Forum) by OneNewBoy on Fri, Mar 22 2013
Pole-Zero analysis (sweep)

Hi everyone I am performing a pole-zero analysis and sweeping a design variable (i.e. the load capacitance) which works works great. but when i am plotting the results using Results>Direct Plot>Main Form>pz i can't interprete the x-axis since it is not labeled and I cant find a reference...

Posted to Custom IC Design (Forum) by Battosai on Mon, Mar 4 2013
How to change wire's collor in Virtuso Schematic Editor

Is it possible to change individual collor for wire in Virtuoso Schematic Editor (rev. 6.1.5)? I need several types of wires to visualize voltage and analog-digital domains. The same question about collor of shapes (e.g. lines in symbol) - is it possible to change their collors individually?

Posted to Custom IC Design (Forum) by Runner on Sun, Mar 3 2013
"Smart Devices" and How They Affect Your Mixed-Signal SOC Verification

We are seeing a huge trend -- the mobile revolution is changing the way we go about our everyday lives. Gone are the days where the term 'Internet' was associated with a PC or Mac. The smartphone revolution has changed how the data is consumed and used by consumers and businesses. For example...

Posted to Mixed-Signal Design (Weblog) by Sathish Bala on Mon, Feb 25 2013
Virtuoso - Wire Bus Connectivity Issue

Hello, I am facing this issue regarding how to connect the wire bus connection to the output connectors. If you look at the attached image below I have clearly named each bus bit to its output but I am still facing error. The screenshot image displaying the error is below Any help would be appreciated...

Posted to Custom IC Design (Forum) by sohaiba on Sun, Feb 17 2013

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Virtuoso

Step a bus signal from ADE-XL design variable

Unleashing Mixed-Signal Tech on Tours (ToTs) in North America

Multi-VDD/Power-Gated Design VerilogIn

Re: Problem in Cadence Virtuoso AC analysis

Power Difference between Analog Simulation and RTL complier estimation

Re: Problem in Cadence Virtuoso AC analysis

Pole-Zero analysis (sweep)

How to change wire's collor in Virtuso Schematic Editor

"Smart Devices" and How They Affect Your Mixed-Signal SOC Verification

Virtuoso - Wire Bus Connectivity Issue