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Virtuoso

Noise sources in PSS analysis

Hi all, I have a pretty simple doubt. I am using Verilog A based circuit netlist to perform circuit simulation in cadence spectre. I have defined some flicker noise sources in the same netlist. If I simulated a simple differential amplifier, I can get the inut referred noise through noise analysis. Now...

Posted to Custom IC Design (Forum) by OneNewBoy on Tue, May 14 2013
Virtuosity: 10 Things I Learned in April by Browsing Cadence Online Support

I'll confess: I didn't learn all of this strictly by browsing http://support.cadence.com (Cadence Online Support). I also wandered over onto http://www.cadence.com/community/blogs/ii (Industry Insights blog) and http://www.cadence.com/cadence/events (Cadence Events), which were well worth a look...

Posted to Custom IC Design (Weblog) by stacyw on Mon, May 13 2013
A CPF User Perspective on IEEE 1801 (UPF) “Methodology Convergence”

By leveraging Common Power Format (CPF) constructs and removing some older Unified Power Format (UPF) commands, the emerging IEEE 1801-2013 standard (UPF 2.1) will help enable "methodology convergence" with CPF. Kamran Haqqani, principal engineer at Maxim Integrated, will be happy to see this...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 13 2013
Netlisting problem in ADE-L: Empty ihnl/cds1,2,3,4

Hi, I am using virtuoso 6.14.504 and have netlisting issues because of empty ihnl/cds1, 2, 3 and 4 directories. This is a design that worked well a few months ago and now as I try to revive that work, I have this issue. I see a populated ihnl/cds0 directory and the netlist and map files in it. The empty...

Posted to Custom IC Design (Forum) by Asavanth on Wed, May 1 2013
Clock Netlist export and import to Cadence Virtuoso

Hi everyone! Does anyone had succeed in importing SPICE Netlist into Cadence Virtuoso? I have tried several times but it seems something is wrong and I can not really get it work. The thing which I am dealing with right now is like this. 1.A design was fully place and route in Cadence Encounter 2.I was...

Posted to Digital Implementation (Forum) by Yuqi on Fri, Apr 26 2013
Using AMS Ultrasim, clock input becomes triangular wave

Hi! The simulator I'm using is AMS and the solver is Ultrasim. My clock generator is a Vsource from analog lib. At the first 55 cycles, the clock input is a square wave. After that it becomes a triangular wave. By any chance, is there some issue with the accuracy options of Ultrasim? Thanks!

Posted to Cadence Academic Network (Forum) by eyec on Fri, Apr 26 2013
GCC_3.3.1 not found (required by /usr/lib/libX11.so.6

Hi, When I do the Verilog XL integratio in virtuoso and try to see the "Viewwaveform" , I do not get any window. Simulation of the verilog file gose fine.

Posted to Mixed-Signal Design (Forum) by KR1089 on Sun, Apr 14 2013
Virtuosity: 10 Things I Learned in March by Browsing Cadence Online Support

Topics in March include advanced analysis in ADE GXL, taking advantage of lots of features for doing statistical analysis in ADE XL, defining bindkeys in ADE L (yes, you can do that!), plus a variety of useful details in the areas of routing and advanced custom layout. Enjoy! Application Notes 1. Design...

Posted to Custom IC Design (Weblog) by stacyw on Thu, Apr 11 2013
Virtuoso Layout: instance boundry

Hello everybody, I sometimes see a strange behaviour when creating a layout in IC6.15: Starting at some time (do not know when/why) doing a fit does fit the layout in the middle of the layout editor, but there is a huge black area around it. So the size of the layout (rectangle form) shown is <<50...

Posted to Custom IC Design (Forum) by MarkusK on Wed, Apr 10 2013
Step a bus signal from ADE-XL design variable

Hi, Is there a way for me to use design variables in ADE-XL to step through all possible values in a bus, say a_signal<3:0>, and run a DC simulation for each step? Regards, Daniel

Posted to Mixed-Signal Design (Forum) by daasboe on Wed, Apr 10 2013

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Virtuoso

Noise sources in PSS analysis

Virtuosity: 10 Things I Learned in April by Browsing Cadence Online Support

A CPF User Perspective on IEEE 1801 (UPF) “Methodology Convergence”

Netlisting problem in ADE-L: Empty ihnl/cds1,2,3,4

Clock Netlist export and import to Cadence Virtuoso

Using AMS Ultrasim, clock input becomes triangular wave

GCC_3.3.1 not found (required by /usr/lib/libX11.so.6

Virtuosity: 10 Things I Learned in March by Browsing Cadence Online Support

Virtuoso Layout: instance boundry

Step a bus signal from ADE-XL design variable